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MAX11120–MAX11128

1Msps, Low-Power, Serial 12-/10-/8-Bit,

4-/8-/16-Channel ADCs

ELECTRICAL CHARACTERISTICS (MAX11120/MAX11123/MAX11126) (continued)

Note 3: Channel ID disabled.

Note 4: Tested in single-ended mode.

Note 5: Offset nulled.

Note 7: Tested and guaranteed with fully differential input.

Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.

Note 10: See Figure 3 (Equivalent Input Circuit).

Note 11: Guaranteed by characterization.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

TIMING CHARACTERISTICS (Figure 1) (Note 11)

SCLK Clock Period

Externally clocked conversion

62.4

ns

SCLK Duty Cycle

40

60

%

SCLK Fall to DOUT Transition

4

16.5

ns

4

15

16th SCLK Fall to DOUT Disable

15

ns

14th SCLK Fall to DOUT Disable

16

ns

SCLK Fall to DOUT Enable

14

ns

DIN to SCLK Rise Setup

4

ns

SCLK Rise to DIN Hold

1

ns

CS Fall to SCLK Fall Setup

4

ns

SCLK Fall to CS Fall Hold

1

ns

CNVST Pulse Width

See Figure 6

5

ns

CS or CNVST Rise to EOC Low

(Note 8)

5.3

6.2

F

s

CS Pulse Width

5

ns