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TPS92070PW Datasheet(PDF) 5 Page - Texas Instruments |
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TPS92070PW Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 20 page  TPS92070 www.ti.com SLUSAN1 – DRAFT 6 * AUGUST 30, 2011 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, −40°C < TA < 125°C, TJ = TA, VVDD = 12 V, GND =0 V, IVZ = 50 μA, RMIN = 71.5 kΩ, CVDD = 4.7µF, CBP = 1 µF, CLP = 220nF PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ERROR AMPLIFIER VIOS Input offset voltage 5 mV < VCS < 100 mV, VCOMP = 3 V ±500 μV VCOMP(min) Minimum COMP clamp voltage VCS = 150 mV, VLP < 3 V 1.45 1.53 1.60 V VCOMP(max) Maximum COMP clamp voltage VCS < 100 mV, VLP > 2.1 V 3.6 3.7 3.8 V VCS(min) Minimum CS reference voltage VLP = 0, RMIN = 71.5 kΩ, TA = 25°C 2.835 3.15 3.465 mV VCS(max) Maximum CS reference voltage VLP > 2.1 V, TA = 25°C 97 100 103 mV MODULATION fCLAMP(max) Maximum frequency clamp Measured at GATE, VCOMP = 3.5 V, TA = 25°C 132 138 146 kHz Measure at GATE, VCOMP = 1.53 V, VVD = 0 V, fCLAMP(min) Minimum frequency clamp 10 20 30 TA = 25°C VALLEY DETECT Measured when GATE is high, IVD = –15 μA –560 VDCLAMP VD clamp mV Measured when GATE is low and VD is falling –125 VVD(en) VD enable threshold Minimum peak of resonant valley, VCOMP = 1.8 V 600 mV VVD(zc) Zero-crossing detect threshold Measured at VD (falling) 80 100 135 mV VCOMP > VMINF_DET, VVD = 0 V, wait time for next tVD(vw) Valley wait timer 10 12.7 14 µs PWM pulse with zero-crossing detected IVD(min) Current required for valley detection –50 µA OVERCURRENT PROTECTION VPCS(oc) Over current limit Measure at PCS (rising), VCOMP = 4 V 670 700 750 mV tPCS_G1(oc) Propagation delay Measured between PCS and GATE falling 10 64 190 ns PWM COMPARATOR tLEB Leading edge blanking Measured at GATE, VCOMP = 3.5 V 180 220 300 ns VPWM(max) VCOMP = VCOMP(max) 600 650 VPWM PWM thresholds VCOMP = 3.5 V 460 500 550 mV VPWM(min) Measured at PCS rising, COMP ≤ 2 V 40 65 80 tPCS_G1(cl) Propagation delay Measured between PCS and GATE falling 10 54 120 ns LED ISOLATED CURRENT SENSE RISO(pd) Pull down resistance GATE is high 240 270 350 Ω PWM OUTPUTS VGATE(oh) Output voltage high 6.7 7 7.2 Measured at GATE V VGATE(ol) Output voltage low –0.01 0 0.01 tFALL(pwm) Fall time CGATE = 1 nF, TA = 25°C 43 70 ns tRISE(pwm) Rise time CGATE = 1 nF, TA = 25°C 105 155 TRIAC DIMMER DETECTION VTDD(oh) Output voltage high Measured at TDD 6.7 7 7.2 V VTDD(ol) Output voltage low –0.01 0 0.01 tFALL(tdd) Fall time CTDD = 1 nF 120 190 ns tRISE(tdd) Rise time CTDD = 1 nF 130 220 Minimum delay from 1V to 5V SEN tDLY_1V_5V signal transitions for no dimmer 105 135 170 µs detection Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s) :TPS92070 |
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