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INA826_1112 Datasheet(PDF) 6 Page - Texas Instruments |
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INA826_1112 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 40 page R G R G +IN +V S V OUT REF 1 2 3 4 8 7 6 5 - IN - V S -IN R G R G +IN +V S V OUT REF -VS 1 2 3 4 8 7 6 5 Exposed Thermal DiePad on Underside INA826 SBOS562B – AUGUST 2011 – REVISED DECEMBER 2011 www.ti.com PIN CONFIGURATIONS DGK PACKAGE DRG PACKAGE MSOP-8, SO-8 3-mm × 3-mm DFN-8 (TOP VIEW) (TOP VIEW) (1) SO-8 and DFN-8 packages are product preview. PIN DESCRIPTIONS NAME NO. DESCRIPTION –IN 1 Negative input RG 2 Gain setting pin. Place a gain resistor between pin 2 and pin 3. RG 3 Gain setting pin. Place a gain resistor between pin 2 and pin 3. +IN 4 Positive input –VS 5 Negative supply REF 6 Reference input. This pin must be driven by low impedance. VOUT 7 Output +VS 8 Positive supply 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): INA826 |
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