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TPD2EUSB30 Datasheet(PDF) 2 Page - Texas Instruments |
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TPD2EUSB30 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 16 page GND D2+ D2- D1+ D1- GND D+ D– TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2A – AUGUST 2010 – REVISED DECEMBER 2010 www.ti.com ORDERING INFORMATION TA PACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOT – DRT Tape and reel TPD2EUSB30DRTR 5PX –40°C to 85°C SOT – DRT Tape and reel TPD2EUSB30ADRTR 5SX SON – DQA Tape and reel TPD4EUSB30DQAR 66R (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. CIRCUIT DIAGRAMS TPD4EUSB30 Circuit TPD2EUSB30/A Circuit TERMINAL FUNCTIONS TERMINAL TYPE DESCRIPTION DRT NAME DQA PIN NO. PIN NO. Dx+, 1, 1,2, High-speed ESD clamp, provides ESD protection to the high-speed differential ESD port Dx– 2 4, 5 data lines GND 3 3, 8 GND Ground 6, 7, N.C. Not normally connected 9, 10 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 |
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