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SI9122E Datasheet(PDF) 8 Page - Vishay Siliconix |
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SI9122E Datasheet(HTML) 8 Page - Vishay Siliconix |
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8 / 20 page  www.vishay.com 8 Document Number: 73866 S-80112-Rev. D, 21-Jan-08 Vishay Siliconix Si9122E DETAILED OPTION Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins to charge up the VCC capacitor. Current into the external VCC capacitor is limited to typically 40 mA by the internal DMOS device. When VCC exceeds the UVLO voltage of 8.8 V a soft-start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals VREG. During this period, between VUVLO and VREG, excessive load current will result in VCC falling below VUVLO and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing of the VCC capacitor, bootstrap capacitor and the soft-start capacitor. The value of the VCC capacitor should therefore be chosen to be capable of maintaining switch mode operation until the required VCC current can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). Feedback from the output of the switch mode supply charges VCC above VREG and fully disconnects the pre-regulator, isolating VCC from VIN. VCC is then maintained above VREG for the duration of switch mode operation. In the event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. Care needs to be taken if there is a delay prior to the external circuit feeding back to the VCC supply. To prevent excessive power dissipation within the IC it is advisable to use an external PNP device. A pin has been incorporated on the IC, (REG_COMP) to provide compensation when employing the external device. In this case the VIN pin is connected to the base of the PNP device and controls the current, while the REG_COMP pin determines the frequency compensation of the circuit. The value of the REG_COMP capacitor cannot be too big, otherwise it will slow down the response of the pre-regulator in the case that fault situations occur and pre-regulator needs to be turned on again. To understand the operation, please refer to figure 5. Figure 4. Detailed Si9122E Block Diagram Timer + – 132 k EP + – Bandgap Reference 3.3 V OSC Loop Control 135 °C Temp Protection High Voltage Interface VSD VUV VUVLO Logic Clock OTP VREF VINDET – + ROSC Oscillator Clock 60 k VREF/2 PWM Generator – + – + VUV VSD VREF 550 mV Logic DH BST LX High-Side Primary Driver DL SRH SRL PGND Low-Side Primary Driver Synchronous Driver (High) Synchronous Driver (Low) BBM Current Control Gain 100 mV CS2 CS1 Blanking CL_CONT VCC 20 µA Soft-Start SS Enable SS Si9122E 8 V – + – + VREG 9.1 V VCC VIN Pre-Regulator VUVLO 8.8 V 9.1 V VCC VCC VCC GND Voltage Feedforward Frequency Foldback CL_CONT 12 V |
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