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SI9102DJ02-E3 Datasheet(PDF) 6 Page - Vishay Siliconix |
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SI9102DJ02-E3 Datasheet(HTML) 6 Page - Vishay Siliconix |
6 / 10 page www.vishay.com 6 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Vishay Siliconix Si9102 DETAIL DESCRIPTION BIAS To properly set the bias for the Si9102, a 390 k Ω resistor should be tied from BIAS to - VIN. This determines the mag- nitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 µA. Reference Section The reference section of the Si9102 consists of a tempera- ture compensated buried zener and trimmable divider net- work. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming proce- dure that is used on the Si9102 brings the output of the error amplifier (which is configured for unity gain during trimming) to within ± 1 % of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external volt- age source can be used to override the internal voltage source, if desired, without otherwise altering the perfor- mance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" com- pensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Oscillator Section The oscillator consists of a ring of CMOS inverters, capaci- tors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC in and OSC out pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to - VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to ≤ 50 % by locking the switching fre- quency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5 V pulse amplitude and 0.5 µs pulse width, typical val- ues would be 100 pF in series with 3 k Ω to OSC IN. SHUTDOWN and RESET SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off when- ever SHUTDOWN is low. By simultaneously having SHUT- DOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Table 1. Truth Table for the SHUTDOWN and RESET Pins Output Switch The output switch is a 7 Ω , 200 V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic body- drain diode. However, the body contact in the Si9102 is con- nected internally to - VIN and is independent of the SOURCE. SHUTDOWN RESET Output H H Normal Operation H Normal Operation (No Change) L H Off (Not Latched) L L Off (Latched) L Off (Latched, No Change) |
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