Pad No.

X

Y

Pad No.

X

Y

Pad No.

X

Y

11

-1512.50

101.25

45

781.30

-1410.00

79

900.60

1407.45

12

-1512.50

6.25

46

876.30

-1410.00

80

805.60

1407.45

13

-1512.50

-88.75

47

971.30

-1410.00

81

710.60

1407.45

14

-1512.50

-183.75

48

1066.30

-1410.00

82

615.60

1407.45

15

-1512.50

-278.75

49

1161.30

-1410.00

83

520.60

1407.45

16

-1512.50

-373.75

50

1256.30

-1410.00

84

425.60

1407.45

17

-1512.50

-468.75

51

1351.30

-1410.00

85

330.60

1407.45

18

-1512.50

-563.75

52

1446.30

-1410.00

86

235.60

1407.45

19

-1512.50

-658.75

53

1512.50

-949.55

87

140.60

1407.45

20

-1512.50

-753.75

54

1512.50

-845.55

88

45.60

1407.45

21

-1512.50

-848.75

55

1512.50

-759.55

89

-49.40

1407.45

22

-1512.50

-943.75

56

1512.50

-664.55

90

-144.40

1407.45

23

-1441.90

-1095.00

57

1512.50

-569.55

91

-239.40

1407.45

24

-1441.90

-1190.00

58

1512.50

-474.55

92

-334.40

1407.45

25

-1441.90

-1295.60

59

1512.50

-379.55

93

-429.40

1407.45

26

-1240.80

-1310.40

60

1512.50

-284.55

94

-524.40

1407.45

27

-1145.80

-1310.40

61

1512.50

-166.15

95

-619.40

1407.45

28

-1040.20

-1310.40

62

1512.50

-71.15

96

-714.40

1407.45

29

-945.20

-1310.40

63

1512.50

23.85

97

-809.40

1407.45

30

-842.00

-1310.40

64

1512.50

118.85

98

-904.40

1407.45

31

-743.30

-1310.40

65

1512.50

213.85

99

-999.40

1407.45

32

-637.70

-1310.40

66

1512.50

308.85

100

-1094.40

1407.45

33

-542.70

-1310.40

67

1512.50

403.85

101

-1189.40

1407.45

34

-437.10

-1310.40

68

1512.50

498.85

102

-1284.40

1407.45

Pad Description

Pad No.

Pad Name

I/O

Description

23

CS

I

Chip selection input with pull-high resistor. When the CS is logic high, the data

and command read from or write to the HT1647A are disabled. The serial inter-

face circuit is also reset. But if the CS is at a logic low level and is input to the CS

pad, the data and command transmission between the host controller and the

HT1647A are all enabled.

24

RD

I

READ clock input with pull-high resistor. Data in the RAM of the HT1647A are

clocked out on the rising edge of the RD signal. The clocked out data will appear

on the data line. The host controller can use the next falling edge to latch the

clocked out data.

25

WR

I

WRITE clock input with pull-high resistor. Data on the DATA line are latched into

the HT1647A on the rising edge of the WR signal.

26~29

DB0~DB3

I/O

Parallel data input/output with a pull-high resistor

30

VSS

¾ Negative power supply for logic circuit, ground

31

OP1

I

Used to select D3, D1 or D2, D0; OP1 input with pull-low resistor.

32

OP2

I

OP2 and OP3 are used to select two of four level gray scale; OP2 input with

pull-high resistor.

33

OSCI

I

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to gen-

erate a system clock. If the system clock comes from an external clock source, the

external clock source should be connected to the OSCI pad. But if an on-chip RC

oscillator is selected, the OSCI and OSCO pads can be left open.

34

OSCO

O

35

OP3

I

OP2 and OP3 are used to select two of four level gray scale ; OP3 input with

pull-high resistor.

HT1647A

Rev. 1.40

4

April 29, 2011

PATENTED