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71M6521FE Datasheet(PDF) 7 Page - Maxim Integrated Products |
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71M6521FE Datasheet(HTML) 7 Page - Maxim Integrated Products |
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7 / 107 page  71M6521DE/DH/FE Data Sheet Rev 2 Page: 7 of 107 List of Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles..................................................................................11 Table 2: CE DRAM Locations for ADC Results......................................................................................................................14 Table 3: Meter Equations. ....................................................................................................................................................14 Table 4: Memory Map...........................................................................................................................................................17 Table 5: Stretch Memory Cycle Width ..................................................................................................................................18 Table 6: Internal Data Memory Map......................................................................................................................................19 Table 7: Special Function Registers Locations .....................................................................................................................19 Table 8: Special Function Registers Reset Values ................................................................................................................20 Table 9: PSW Register Flags.................................................................................................................................................21 Table 10: PSW Bit Functions.................................................................................................................................................21 Table 11: Port Registers .......................................................................................................................................................22 Table 12: Special Function Registers....................................................................................................................................23 Table 13: Baud Rate Generation............................................................................................................................................24 Table 14: UART Modes .........................................................................................................................................................24 Table 15: The S0CON Register.............................................................................................................................................24 Table 16: The S1CON register..............................................................................................................................................25 Table 17: The S0CON Bit Functions .....................................................................................................................................25 Table 18: The S1CON Bit Functions .....................................................................................................................................25 Table 19: The TCON Register ..............................................................................................................................................26 Table 20: The TCON Register Bit Functions..........................................................................................................................26 Table 21: The TMOD Register..............................................................................................................................................27 Table 22: TMOD Register Bit Description............................................................................................................................27 Table 23: Timers/Counters Mode Description ......................................................................................................................27 Table 24: Timer Modes .........................................................................................................................................................28 Table 25: The PCON Register ..............................................................................................................................................28 Table 26: PCON Register Bit Description.............................................................................................................................28 Table 27: The IEN0 Register (see also Table 32) .................................................................................................................29 Table 28: The IEN0 Bit Functions (see also Table 32)..........................................................................................................29 Table 29: The IEN1 Register (see also Tables 30/31) ..........................................................................................................29 Table 30: The IEN1 Bit Functions (see also Tables 30/31)...................................................................................................29 Table 31: The IP0 Register (see also Table 45)....................................................................................................................29 Table 32: The IP0 bit Functions (see also Table 45).............................................................................................................30 Table 33: The WDTREL Register .........................................................................................................................................30 Table 34: The WDTREL Bit Functions..................................................................................................................................30 Table 35: The IEN0 Register ................................................................................................................................................31 Table 36: The IEN0 Bit Functions.........................................................................................................................................31 Table 37: The IEN1 Register ................................................................................................................................................31 Table 38: The IEN1 Bit Functions.........................................................................................................................................31 Table 39: The IEN2 Register ................................................................................................................................................32 Table 40: The IEN2 Bit Functions.........................................................................................................................................32 Table 41: The TCON Register ..............................................................................................................................................32 Table 42: The TCON Bit Functions.......................................................................................................................................32 Table 43: The T2CON Bit Functions.....................................................................................................................................32 Table 44: The IRCON Register.............................................................................................................................................33 Table 45: The IRCON Bit Functions .....................................................................................................................................33 Table 46: External MPU Interrupts........................................................................................................................................33 Table 47: Interrupt Enable and Flag Bits ..............................................................................................................................34 Table 48: Priority Level Groups ............................................................................................................................................35 Table 49: The IP0 Register ...................................................................................................................................................35 Table 50: The IP1 Register: ..................................................................................................................................................35 Table 51: Priority Levels .......................................................................................................................................................35 Table 52: Interrupt Polling Sequence....................................................................................................................................36 Table 53: Interrupt Vectors ...................................................................................................................................................36 Table 54: Data/Direction Registers and Internal Resources for DIO Pin Groups..................................................................41 |
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