HI-5111PCIF datasheet(3/51 Pages) HOLTIC

Part #	HI-5111PCIF

Description	CAN Controller with Integrated Transceiver

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Manufacturer	HOLTIC [Holt Integrated Circuits]

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HI-5110

SIGNAL

FUNCTION

DESCRIPTION

INTERNAL PULL UP / DOWN

SCK

INPUT

SPI Clock. Data is shifted into or out of the SPI interface using SCK

50K ohm pull-down

INPUT

Chip Select. Data is shifted into SI and out of SO when

is low.

50K ohm pull-up

SI

INPUT

SPI interface serial data input

50K ohm pull-down

SO

OUTPUT

SPI interface serial data output

INT

OUTPUT

Active high. Programmable interrupt output

STAT

OUTPUT

Active high. Programmable status output.

TXEN

INPUT

0K ohm pull-down

OSCIN

INPUT

Crystal input. A parallel resonant crystal can be connected between OSCIN and

OSCOUT. If an external clock is used, it should be connected to the OSCIN pin

and the OSCOUT pin should be left floating. The internal oscillator should be

shut off by setting the OSCOFF bit in the CTRL1 register.

OSCOUT

OUTPUT

Crystal output. If an external clock is used, this pin should be left floating and

disabled by setting the OSCOFF bit in the CTRL1 register.

GP1

OUTPUT

General purpose pin 1, which can be programmed to reflect the values of

interrupt and status flag bits.

GP2

OUTPUT

General purpose pin 2, which can be programmed to reflect the values of

interrupt and status flag bits.

CLKOUT

OUTPUT

Clock output pin with programmable frequency divider.

SPLIT

OUTPUT

VDD/2 output bias (Powered off in Sleep Mode and when the common mode

bias is greater than 25V).

CANH

BUS I/O

CAN bus line high.

CANL

BUS I/O

CAN bus line low.

MR

INPUT

Active High. Device Master Reset input pin. Asserting this pin resets all registers

50K ohm pull-down

and memory buffers to their default state at start-up.

VDD

POWER

5V supply voltage input.

GND

POWER

Supply voltage ground.

CS

Active high. Transmit Enable pin. When the TXEN pin is asserted, any message

10

in the Transmit FIFO will be automatically loaded to the Transmit buffer and sent

if the bus is available. This pin is logically ORed with the TXEN and TX1M bits

in the CTRL1 register. When the TXEN pin is reset, messages loaded to the

FIFO will not be sent until TXEN or TX1M bits are set in the CTRL1 register.

VLOGIC

POWER

3.3V supply voltage input. This supply is used to drive the host digital logic I/O.

It can either be connected directly to VDD (+5V) or a +3.3V supply.

PIN DESCRIPTIONS

HOLT INTEGRATED CIRCUITS

3

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