SIGNAL

FUNCTION

DESCRIPTION

Internal

Pull-up / Down

NOCONV

INPUT

Disables on-chip DC-DC voltage converter

50KΩ pull-down

RINB-40

INPUT

Alternate receiver negative input. Requires external 40K ohm resistor

RINB

INPUT

Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP)

RINA

INPUT

Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP)

RINA-40

INPUT

Alternate receiver positive input. Requires external 40K ohm resistor

GND

POWER

Chip 0V Supply (All GND pins on package must be connected)

TFIFO

OUTPUT

Output is user programmable to indicate the Transmit FIFO Full or Half-full state.

See FSPIN<5>, in Table 7, FIFO Status Pin Assignment Register.

TEMPTY

OUTPUT

Output goes high when the transmit FIFO is empty

INSYNC

OUTPUT

Output goes high when the receiver is synchronized to the incoming data. Synchroni-

zation occurs at the next valid sync mark following the detection of the proper

number and order of consecutively spaced sync marks. See Table 3.

SYNC0

OUTPUT

Output in conjunction with SYNC1 output indicates when each of the four ARINC 717

subframe sync words are received. Only valid when the INSYNC pin is high.

SYNC1

OUTPUT

Output in conjunction with SYNC0 output indicates when each of the four ARINC 717

subframe sync words are received. Only valid when the INSYNC pin is high.

MATCH

OUTPUT

Output goes high when the value of the Frame Word Count Register matches the

value in the Frame Count Utility Register, WRDCNT.

RFIFO

OUTPUT

Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty

state. See FSPIN<7:6> in Table 7, FIFO Status Pin Assignment Register.

ROVF

OUTPUT

Receive FIFO Overflow. Output goes high when an attempt is made to load a full

Receive FIFO

MR

INPUT

Master Reset, active low

50KΩ pull-up

RSEL

INPUT

Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0

50KΩ pull-down

SI

INPUT

SPI interface serial data input

50KΩ pull-down

SCK

INPUT

SPI Clock. Data is shifted into SI and out of SO when

is low.

CS

50KΩ pull-down

SO

OUTPUT

SPI Interface seral data output

CS

INPUT

Chip Select. Data is shifted into SI and out of SO using SCK when

is low

CS

50KΩ pull-up

ACLK

INPUT

Master timing source for receiver and transmitters. 24 MHZ ±0.1%

50KΩ pull-down

TXBB

OUTPUT

Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required)

OUTBB

OUTPUT

Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external

32.5 ohm resistor

TXOUTBB

OUTPUT

Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717

bus

TXOUTBA

OUTPUT

Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC

717 bus

OUTBA

OUTPUT

Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external

32.5 ohm resistor

TXBA

OUTPUT

Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required)

TXHB

OUTPUT

Harvard Bi-Phase (HBP) digital low output (external line driver required)

OUTHB

OUTPUT

Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5

ohm resistor

TXOUTHB

OUTPUT

Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus

TXOUTHA

OUTPUT

Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus

OUTHA

OUTPUT

Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5

ohm resistor

TXHA

OUTPUT

Harvard Bi-Phase (HBP) digital high output (external line driver required)

V-

CONVERTER

DC/DC converter negative voltage

C2-

CONVERTER

DC/DC converter fly capacitor for V-

C2+

CONVERTER

DC/DC converter fly capacitor for V-

V+

CONVERTER

DC/DC converter positive voltage

C1+

CONVERTER

DC/DC converter fly capacitor for V+

C1-

CONVERTER

DC/DC converter fly capacitor for V+

VDD

POWER

Chip +3.3V Supply

TA B L E 1 .

PIN DESCRIPTIONS

HOLT INTEGRATED CIRCUITS

3

HI-3717