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LE25FU206 Datasheet(PDF) 6 Page - Sanyo Semicon Device

Part # LE25FU206
Description  2M-bit (256K횞8) Serial Flash Memory
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Manufacturer  SANYO [Sanyo Semicon Device]
Direct Link  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LE25FU206 Datasheet(HTML) 6 Page - Sanyo Semicon Device

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LE25FU206
No.A1191-6/21
Description of Commands and Their Operations
"Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and
operations corresponding to each command is presented below.
1. Read
There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first
through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the
designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus
cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms.
Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.
"Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the
dummy bits in the fifth bus cycle are input.
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding
data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address
(3FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
Figure 5-a 4 Bus Read
Figure 5-b 5 Bus Read
N+2
N+1
N
CS
High Impedance
DATA
DATA
DATA
SCK
SO
SI
03h
Add.
Add.
Add.
15
MSB
MSB
MSB
0
1
2
3
4
5
6
7
8
23
16
24
31
39
47
8CLK
Mode0
Mode3
32
40
N+2
N+1
N
CS
High Impedance
DATA
DATA
DATA
SCK
SO
SI
0Bh
Add.
Add.
Add.
X
15
MSB
MSB
MSB
0
1
2
3
4
5
6
7
8
23
16
24
31 32
39 40
47 48
55
Mode3
Mode0
8CLK


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