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LC89057W-VF4A-E Datasheet(PDF) 8 Page - Sanyo Semicon Device |
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LC89057W-VF4A-E Datasheet(HTML) 8 Page - Sanyo Semicon Device |
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8 / 59 page  LC89057W-VF4A-E No.7202-8/59 8.4 AC Characteristics Table 8.4: AC Characteristics at Ta=-30 to 70°C, AVDD=DVDD=3.0 to 3.6V, AGND=DGND=0V Ratings Parameter Symbol Conditions min typ max Unit RX0 to RX6 sampling frequency fRFS 28 195 kHz XIN clock frequency fXF1 8-4-1 8 12.288 19 MHz XIN clock frequency fXF2 8-4-2 20 24.576 30 MHz RMCK clock frequency fRCK 4 100 MHz RMCK clock jitter tj 200 ps RMCK, RBCK delay tMBO 10 ns RBCK, RDATA delay tBDO 10 ns RMCK, SBCK delay tMBO 8-4-3 10 ns SBCK, RDATA delay tBDO 8-4-4 10 ns TMCK input pulse width tWMI 10 ns RX*, TMCK delay tRDI 1/4TMCK ns TBCK input pulse width tWBI 40 ns TLRCK sampling frequency tTFS 28 195 kHz TBCK, TDATA setup tDSI 20 ns TBCK, TDATA hold tDHI 20 ns TMCK, TBCK delay tMBI 8-4-5 10 ns TBCK, TDATA delay tBDI 10 ns 8-4-1: XINSEL = 0 setting, 12.288MHz must be set when calculating input sampling frequency 8-4-2: XINSEL =1 setting, 24.576MHz must be set when calculating input sampling frequency 8-4-3: When RMCK and SBCK source clocks are identical 8-4-4: When SBCK is the PLL source clock 8-4-5: TCKSEL = 0 setting (256fs), the falling edge of TBCK is in synchronization with the rising edge of TMCK. TCKSEL = 1 setting (128fs), the falling edge of TBCK is in synchronization with the falling edge of TMCK. Figure 8.1 AC Characteristics tWBI tWBI TBCK (I) TDATA (I) TLRCK (I) tDSI tDHI tBDI TMCK (I) RBCK (O) RDATA (O) RLRCK (O) tBDO RMCK (O) tMBO tMBI tWMI RX* (I) tRDI |
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