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HT82B60R Datasheet(PDF) 35 Page - Holtek Semiconductor Inc |
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HT82B60R Datasheet(HTML) 35 Page - Holtek Semiconductor Inc |
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35 / 70 page  HT82B60R Rev. 1.10 35 February 1, 2011 The MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the desired endpoint FIFO. The MISC will be cleared by the USB reset signal. Bit No. Label R/W Function 0 REQ R/W After setting the other status of the desired one in the MISC, endpoint FIFO can be requested by setting this bit to ²1². After the task is completed, this bit must be cleared to ²0². 1 TX R/W This bit defines the direction of data transferring between the MCU and endpoint FIFO. When the TX is set to ²1², this means that the MCU wants to write data to the endpoint FIFO. After the task is completed, this bit must be cleared to ²0² before ter- minating the request to represent the end of transferring. For a read action, this bit has to be cleared to ²0² to represent that MCU wants to read data from the endpoint FIFO and has to be set to ²1² after completion. 2 CLEAR R/W Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready. 4 3 SELP1 SELP0 R/W Defines which endpoint FIFO is selected, SELP1,SELP0: 00: endpoint FIFO0 01: endpoint FIFO1 10: endpoint FIFO2 11: endpoint FIFO3 5 SCMD R/W Used to show that the data in the endpoint FIFO is a SETUP command. This bit has to be cleared by firmware. That is to say, even if the MCU is busy, the device will not miss any SETUP commands from the host. 6 READY R Read only status bit, this bit is used to indicate that the desired endpoint FIFO is ready for operation. 7 LEN0 R/W Used to indicate that a 0-sized packet has been sent from a host to the MCU. This bit should be cleared by firmware. MISC (46H) Register The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which the address is listed in the following table. After reading the current data, the next data will show after 2 ms, this is used to check the endpoint FIFO status and response to the MISC register, if the read/write action is still going on. Registers R/W Address Bit7~Bit0 FIFO0 R/W 48H Data7~Data0 FIFO1 R/W 49H Data7~Data0 FIFO2 R/W 4AH Data7~Data0 FIFO3 R/W 4BH Data7~Data0 There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform read- ing, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writ- ing and clearing. Actions MISC Setting Flow and Status Read FIFO0 sequence 00H ®01H®delay 2ms, check 41H®read* from FIFO0 register and check not ready (01H) ®03H®02H Write FIFO0 sequence 02H ®03H®delay 2ms, check 43H®write* to FIFO0 register and check not ready (03H) ®01H®00H Check whether FIFO0 can be read or not 00H ®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H Check whether FIFO0 can be written or not 02H ®03H®delay 2ms, check 43H (ready) or 03H (not ready)®02H Write 0-sized packet sequence to FIFO0 02H ®03H®delay 2ms, check 43H®01H®00H Clear FIFO1 sequence 01H ®delay 2ms®05H®delay 2ms®00H Note: *: There is a 2 ms time between 2 read actions or between 2 write actions. |
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