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1145M Datasheet(PDF) 10 Page - Sanyo Semicon Device |
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1145M Datasheet(HTML) 10 Page - Sanyo Semicon Device |
10 / 17 page 1) Current path during detuning 2) Current return path from detuning As can be seen from the above circuit diagrams, the time constant during detuning is determined by the internal PNP resistance, the NPN collector resistance and the capacitance of the externally- mounted capacitor. This time constant is determined by the external resistance RAFC and capacitor C. This time constant, τ =RAFC × C, must be set depending on the required search time. 3. Narrow-band SD output circuit An IF count circuit is provided for equipment compatibility for the European marketplace. However, if the band is made narrow using only the SD circuit, there is a tendency for the number of erroneous stops caused by an undesired signal to increase. To prevent this, two threshold voltages should be used to control the SD circuit. The input/output current from pin 8 becomes zero during return. SD output SD sensitivity setting Mute driver pin for the 2nd threshold voltage. Band Mute Characteristics (1) Without C17 Frequency, Δf – kHz Band Mute Characteristics (2) With C17 = 10000 pF Frequency, Δf – kHz LA1145, 1145M No. 2725-10/17 |
Similar Part No. - 1145M |
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Similar Description - 1145M |
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