1)

Current path during detuning

2)

Current return path from detuning

As can be seen from the above circuit diagrams, the time constant during detuning is determined by the internal PNP

resistance, the NPN collector resistance and the capacitance of the externally- mounted capacitor. This time constant is

required search time.

3.

Narrow-band SD output circuit

An IF count circuit is provided for equipment compatibility for the European marketplace. However, if the band is made

narrow using only the SD circuit, there is a tendency for the number of erroneous stops caused by an undesired signal to

increase. To prevent this, two threshold voltages should be used to control the SD circuit.

The input/output current from pin 8 becomes zero during return.

SD output

SD sensitivity setting

Mute driver pin for the 2nd threshold voltage.

Band Mute Characteristics (1)

Frequency,

Δf – kHz

Band Mute Characteristics (2)

Frequency,

Δf – kHz

LA1145, 1145M

No. 2725-10/17