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FM25V10-G Datasheet(PDF) 2 Page - Ramtron International Corporation |
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FM25V10-G Datasheet(HTML) 2 Page - Ramtron International Corporation |
2 / 16 page FM25V10 - 1Mb SPI FRAM Rev. 2.0 May 2010 Page 2 of 16 Instruction Decode Clock Generator Control Logic Write Protect Instruction Register Address Register Counter 16384 x 64 FRAM Array 17 Data I/O Register 8 Nonvolatile Status Register 3 W S C Q D HOLD Figure 1. Block Diagram Pin Descriptions Pin Name I/O Description /S Input Chip Select: This active-low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the C signal. A falling edge on /S must occur prior to every op-code. C Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 40 MHz and may be interrupted at any time. /HOLD Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on C or /S. All transitions on /HOLD must occur while C is low. This pin has a weak internal pull-up (see RIN spec, pg 11). However, if it is not used, the /HOLD pin should be tied to VDD. /W Input Write Protect: This active-low pin prevents write operations to the Status Register only. A complete explanation of write protection is provided on pages 6 and 7. If it is not used, the /W pin should be tied to VDD. D Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of C and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. * D may be connected to Q for a single pin data interface. Q Output Serial Output: This is the data output pin. It is driven during a read and remains tri- stated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock. * Q may be connected to D for a single pin data interface. VDD Supply Power Supply VSS Supply Ground |
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