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25ETS12STRRPBF Datasheet(PDF) 6 Page - Vishay Siliconix

Part # 25ETS12STRRPBF
Description  Input Rectifier Diode, 25 A
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Manufacturer  VISHAY [Vishay Siliconix]
Direct Link  http://www.vishay.com
Logo VISHAY - Vishay Siliconix

25ETS12STRRPBF Datasheet(HTML) 6 Page - Vishay Siliconix

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Document Number: 95046
For technical questions within your region, please contact one of the following:
www.vishay.com
Revision: 31-Mar-11
DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
D2PAK
Outline Dimensions
Vishay Semiconductors
DIMENSIONS in millimeters and inches
Notes
(1) Dimensioning and tolerancing per ASME Y14.5 M-1994
(2) Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at
the outmost extremes of the plastic body
(3) Thermal pad contour optional within dimension E, L1, D1 and E1
(4) Dimension b1 and c1 apply to base metal only
(5) Datum A and B to be determined at datum plane H
(6) Controlling dimension: inch
(7) Outline conforms to JEDEC outline TO-263AB
SYMBOL
MILLIMETERS
INCHES
NOTES
SYMBOL
MILLIMETERS
INCHES
NOTES
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
8.00
0.270
0.315
3
A1
0.00
0.254
0.000
0.010
E
9.65
10.67
0.380
0.420
2, 3
b
0.51
0.99
0.020
0.039
E1
7.90
8.80
0.311
0.346
3
b1
0.51
0.89
0.020
0.035
4
e
2.54 BSC
0.100 BSC
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
4
L
1.78
2.79
0.070
0.110
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
3
c1
0.38
0.58
0.015
0.023
4
L2
1.27
1.78
0.050
0.070
c2
1.14
1.65
0.045
0.065
L3
0.25 BSC
0.010 BSC
D
8.51
9.65
0.335
0.380
2
L4
4.78
5.28
0.188
0.208
c
B
Detail A
c2
A
A
A
± 0.004
B
M
A
Lead tip
(3)
(3)
View A - A
(E)
(D1)
E1
B
H
A1
Detail “A”
Rotated 90 °CW
Scale: 8:1
L
Gauge
plane
0° to 8°
L3
L4
Seating
plane
Section B - B and C - C
Scale: None
(4)
(4)
(b, b2)
b1, b3
(c)
c1
Base
Metal
Plating
Conforms to JEDEC outline D2PAK (SMD-220)
13
2
D
C
A
L2
E
(2)(3)
(2)
4
H
BB
2 x b
2 x b2
L1
0.010
A
B
MM
(3)
e
2 x
Pad layout
MIN.
11.00
(0.43)
MIN.
9.65
(0.38)
MIN.
3.81
(0.15)
MIN.
2.32
(0.08)
17.90 (0.70)
15.00 (0.625)
2.64 (0.103)
2.41 (0.096)
Lead assignments
Diodes
1. - Anode (two die)/open (one die)
2., 4. - Cathode
3. - Anode


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