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TMS320DM8148 Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320DM8148 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 360 page  TMS320DM8148, TMS320DM8147, TMS320DM8146 www.ti.com SPRS647B – MARCH 2011 – REVISED SEPTEMBER 2011 SEE ADDITIONS/MODIFICATIONS/DELETIONS Table 8-12, Ethernet MAC Switch Registers: • Deleted ALE_PORTCTL3, ALE_PORTCTL4, ALE_PORTCTL5 (HEX ADDRESS RANGE: 0x4A10 064C, 0x4A10 0650, 0x4A10 0654, respectively) Section 8.6.1 • Added reference to the MDIO Registers at EMAC HEX ADDRESS RANGE 0x4A10 0800 through EMAC Peripheral 0x4A10 08FF Register Descriptions • Added missing EMAC registers at EMAC HEX ADDRESS RANGE 0x4A10 0900 through 0x4A10 0984 [Cleared E2E Issue] Table 8-18, Timing Requirements for EMAC[x]_RMREFCLK - RMII Operation: Section 8.6.2.2 EMAC RMII Electrical • Updated/Changed the MAX value for parameter NO. 4, tt(RMREFCLK), Transition time, Data/Timing EMAC[x]_RMREFCLK from "TBD" to "3" ns Table 8-25, MDIO Registers: Section 8.6.3.1 • Added RESERVED row at HEX ADDRESS RANGE 0x4A10 088C through 0x4A10 08FF MDIO Peripheral Register Descriptions Section 8.10 Section 8.10, High-Definition Video Processing Subsystem (HDVPSS): High-Definition Video • Deleted "mosaic support", "region-based", and "region based" from the peripheral features bulleted Processing Subsystem list (HDVPSS) Section 8.10.1, HDVPSS Electrical Data/Timing: • Updated/Changed the VOUT[x]_CLK signal to be negative-edge clocking Table 8-41, Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output: • Updated/Changed PARAMETER NO. 6, td(CLK-x), "Delay time, VOUT[x]_CLK to control valid" to "Delay time, VOUT[x]_CLK low (falling) to control valid" • Updated/Changed PARAMETER NO. 6, td(CLK-x), "Delay time, VOUT[x]_CLK to data valid" to "Delay time, VOUT[x]_CLK low (falling) to data valid" • Updated/Changed the MIN value for parameter NO. 6, td(CLK-x), Delay time, VOUT[x]_CLK low Section 8.10 (falling) to control valid from "0.5" to "-1.6" ns. High-Definition Video Processing Subsystem • Updated/Changed the MAX value for parameter NO. 6, td(CLK-x), Delay time, VOUT[x]_CLK low (HDVPSS) (falling) to control valid from "5" to "1.4" ns. • Updated/Changed the MIN value for parameter NO. 6, td(CLK-x), Delay time, VOUT[x]_CLK low (falling) to data valid from "0.5" to "-1.6" ns. • Updated/Changed the MAX value for parameter NO. 6, td(CLK-x), Delay time, VOUT[x]_CLK low (falling) to data valid from "5" to "1.4" ns. Updated/Changed Figure 8-38, HDVPSS Clock Timing Updated/Changed Figure 8-40, HDVPSS Output Timing Section 8.11.2, I2C Electrical Data/Timing: • Updated/Changed the Table 8-44, Timing Requirements for I2C Input Timings Section 8.11.2 • Updated/Changed the Table 8-45, Switching Characteristics Over Recommended Operating I2C Electrical Data/Timing Conditions for I2C Output Timings Table 8-50, Compatible JEDEC DDR2 Devices: Section 8.13.1.1 • Added "(Per Interface)" to the table title DDR2 Routing Guidelines Table 8-63, Compatible JEDEC DDR3 Devices: • Added "(Per Interface)" to the table title Section 8.13.1.2 • Updated/Changed the MAX value for parameter NO. 3, JEDEC DDR3 device count from "8" to "4" DDR3 Routing Guidelines Devices Added "or up to 15 hard disk drives using a Port Multiplier" to "The Serial ATA (SATA) peripheral Section 8.18 provides ..." paragraph Serial ATA Controller (SATA) Copyright © 2011, Texas Instruments Incorporated Contents 9 Submit Documentation Feedback Product Folder Link(s): TMS320DM8148 TMS320DM8147 TMS320DM8146 |
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