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OMAP-L132 Datasheet(PDF) 7 Page - Texas Instruments |
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OMAP-L132 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 227 page  OMAP-L132 www.ti.com SPRS762 – AUGUST 2011 Table 2-1. Characteristics of OMAP-L132 (continued) HARDWARE FEATURES OMAP-L132 Product Preview (PP), Product Status(1) Advance Information (AI), 200 MHz versions - PD or Production Data (PD) (1) ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.2 Device Compatibility The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc. The C674x DSP core is code-compatible with the C6000 ™ DSP platform and supports features of both the C64x+ and C67x+ DSP families. 2.3 ARM Subsystem The ARM Subsystem includes the following features: • ARM926EJ-S RISC processor • ARMv5TEJ (32/16-bit) instruction set • Little endian • System Control Co-Processor 15 (CP15) • MMU • 16KB Instruction cache • 16KB Data cache • Write Buffer • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) • ARM Interrupt controller 2.3.1 ARM926EJ-S RISC CPU The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including: • ARM926EJ -S integer core • CP15 system control coprocessor • Memory Management Unit (MMU) • Separate instruction and data caches • Write buffer • Separate instruction and data (internal RAM) interfaces • Separate instruction and data AHB bus interfaces • Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) Copyright © 2011, Texas Instruments Incorporated Device Overview 7 Submit Documentation Feedback Product Folder Link(s): OMAP-L132 |
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