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ADS1298IPAG Datasheet(PDF) 35 Page - Texas Instruments |
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ADS1298IPAG Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 88 page  STAR co TOp de STARTPin DN I 4/f CLK DRDY or t DR t SETTLE ADS1294, ADS1294R ADS1296, ADS1296R ADS1298, ADS1298R www.ti.com SBAS459H – JANUARY 2010 – REVISED OCTOBER 2011 Reset (RESET) There are two methods to reset the ADS129x: pull the RESET pin low, or send the RESET opcode command. When using the RESET pin, take it low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset it takes 18 tCLK cycles to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever registers CONFIG1 and RESP are set to new values with a WREG command. START The START pin must be set high or the START command sent to begin conversions. When START is low or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversion, hold the START pin low. The ADS129x feature two modes to control conversion: continuous mode and single-shot mode. The mode is selected by SINGLE_SHOT (bit 3 of the CONFIG4 register). In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). Settling Time The settling time (tSETTLE) is the time it takes for the converter to output fully settled data when START signal is pulled high. Once START is pulled high, DRDY is also pulled high. The next falling edge of DRDY indicates that data are ready. Figure 40 shows the timing diagram and Table 9 shows the settling time for different data rates. The settling time depends on fCLK and the decimation ratio (controlled by the DR[2:0] bits in the CONFIG1 register). Table 8 shows the settling time as a function of tCLK. Note that when START is held high and there is a step change in the input signal, it takes 3 × tDR for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. This time must be considered when trying to measure narrow PACE pulses for PACE detection. Figure 40. Settling Time Table 9. Settling Times for Different Data Rates DR[2:0] HIGH-RESOLUTION MODE LOW-POWER MODE UNIT 000 296 584 tCLK 001 584 1160 tCLK 010 1160 2312 tCLK 011 2312 4616 tCLK 100 4616 9224 tCLK 101 9224 18440 tCLK 110 18440 36872 tCLK Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Link(s): ADS1294 ADS1294R ADS1296 ADS1296R ADS1298 ADS1298R |
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