 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GS9091B Datasheet(PDF) 10 Page - Gennum Corporation |
|
||||||||||||||||||||||||||||||
GS9091B Datasheet(HTML) 10 Page - Gennum Corporation |
|
|
10 / 71 page  GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 10 of 71 Proprietary & Confidential K3 IOPROC_EN Non Synchronous Input CONTROL SIGNAL INPUT Signal Levels are LVCMOS / LVTTL compatible. Used to enable or disable the I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: • Illegal Code Remapping • EDH CRC Error Correction • Ancillary Data Checksum Error Correction • TRS Error Correction • EDH Flag Detection To enable a subset of these features, keep IOPROC_EN HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the device will enter low-latency mode. NOTE: When the internal FIFO is configured for Video mode or Ancillary Data Extraction mode, IOPROC_EN must be set HIGH (see Section 3.10). K4 RESET Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to reset the internal operating conditions to default setting or to reset the JTAG test sequence. Host Mode (JTAG_EN = LOW): When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance. When set HIGH, normal operation of the device resumes 10usec after the LOW-to-HIGH transition of the RESET signal. JTAG Test Mode (JTAG_EN = HIGH): When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. K5 SCLK_TCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Clock / Test Clock. All JTAG / Host Interface address and data are shifted into/out of the device synchronously with this clock. Host Mode (JTAG_EN = LOW): SCLK_TCK operates as the host interface serial data clock, SCLK. JTAG Test Mode (JTAG_EN = HIGH): SCLK_TCK operates as the JTAG test clock, TCK. Table 1-1: Ball List and Description (Continued) Ball Name Timing Type Description |
Similar Part No. - GS9091B |
|
Similar Description - GS9091B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
