14583 - 04

5 of 9

33

RESET

I

Resets the scrambler when asserted.

34

-

Most positive power supply connection for analog circuits.

35

-

Most negative power supply connection for analog circuits.

36, 38

I

Differential VCO current setting resistor that sets the VCO frequency.

39, 43

-

Most negative power supply connection (substrate).

40

LBWC

I

TTL level loop bandwidth control that adjusts the PLL bandwidth to optimize for lowest

41, 42

LF+, LF-

I

Differential loop filter pins to optimize loop transfer performance at low loop bandwidths

(NC if not used).

44

SYNC DIS

I

Sync detect disable. Logic high disables sync detection. Logic low allows 8 bit operation

by mapping 000-003 to 000 and 3FC-3FF to 3FF.

PIN DESCRIPTIONS

NUMBER

SYMBOL

TYPE

DESCRIPTION