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TPS40400RHLR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS40400RHLR Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 72 page  TPS40400 SLUS930B – APRIL 2011 – REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply for –40°C ≤ TJ ≤ 125°C, VDD= 12 Vdc, FREQUENCY_SWITCH = 600 kHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VOLTAGE MARGINING VFB slope during margin voltage transition (8) Factory default settings 250 214 188 V/s MRGSLP Accuracy 3 V < VVDD < 20 V, 600 μs < tSS < 9 ms –15% 15% VFBMH FB pin voltage after margin high command Factory default settings 650 660 670 mV VFBML FB pin voltage after margin low command Factory default settings 532 540 548 mV VFBM(max) Maximum FB pin voltage with Margin –40°C < TJ < 125°C 742 750 758 mV VFBM(min) Minimum FB pin voltage with Margin –40°C < TJ < 125°C 445 450 455 mV VFB(inc) Resolution of FB steps with margin 2.34 mV OVERVOLTAGE AND UNDERVOLTAGE DETECTION FB pin overvoltage threshold (OV flag) Factory default settings 638 672 705 VOV mV Accuracy 3 V < VVDD < 20 V, 648 mV < VOV < 690 mV –5% 5% FB pin undervoltage threshold (UV flag) Factory default settings 502 528 554 VUV mV 3 V < VVDD < 20 V, Accuracy –5% 5% 510 mV < VOV < 552 mV PMBus INTERFACE VIH High-level input voltage, CLK, DATA, CNTL 2.1 V VIL Low-level input voltage, CLK, DATA, CNTL 0.8 V High-level input current, CLK, DATA, CNTL –10 10 IIH μA CNTL –12 10 Low-level input current, CLK, DATA, CNTL –10 10 IIL μA CNTL –12 10 VOL Low-level output voltage, DATA, SMBALRT 3.0 V ≤ VVDD ≤ 20 V, IOUT = 2 mA 0.4 V High-level open drain leakage current, DATA, IOH VOUT = 3.6 V 0 10 μA SMBALRT CO (8) Pin capacitance, CLK, DATA 0.7 pF fPMB PMBus operating frequency range Slave mode 10 400 kHz tBUF Bus free time between START and STOP(8) 4.7 μs tHD:STA Hold time after repeated START(8) 4.0 μs tSU:STA Repeated START setup time(8) 4.7 μs tSU:STO STOP setup time(8) 4.0 μs Receive mode 0 tHD:DAT Data hold time(8) ns Transmit mode 300 tSU:DAT Data setup time(8) 250 ns tTIMEOUT Error signal/detect(8) 25 35 μs tLOW:MEXT Cumulative clock low master extend time(8) 50 μs tLOW:SEXT Cumulative clock low slave extend time(8) 25 μs tLOW Clock low time(8) 4.7 μs tHIGH Clock high time(8) 4.0 μs tFALL CLK/DATA fall time(8) 300 ns tRISE CLK/DATA rise time(8) 1000 ns PMBus ADDRESSING IADD ADDX pin current 8.23 9.75 11.21 μA VADD(L) Address pin illegal low voltage threshold 0.055 V (8) Ensured by design. Not production tested. 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS40400 |
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