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TPS40400_1110 Datasheet(PDF) 8 Page - Texas Instruments |
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TPS40400_1110 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 72 page  1 2 3 4 5 6 7 8 9 12 24 13 23 22 21 20 19 18 17 16 15 14 ADDR0 ADDR1 VDD HDRV BOOT SW LDRV GND BP6 SMBALRT 10 11 SYNC CNTL ISNS– VSNS– VSNS+ DIFFO PGOOD TRACK COMP FB DATA CLK TPS40400 BP3 ISNS+ PowerPAD TM SGND TPS40400 SLUS930B – APRIL 2011 – REVISED OCTOBER 2011 www.ti.com DEVICE INFORMATION RHL PACKAGE BOTTOM VIEW PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. Low-order address pin for PMBus address configuration. One of eight resistor values must be connected from ADDR0 21 I this pin to SGND to select the low-order octal digit in the PMBus address. High-order address pin for PMBus address configuration. One of eight resistor values must be connected from ADDR1 22 I this pin to SGND to select the high-order octal digit in the PMBus address. Gate drive voltage for the high-side N-channel MOSFET. A capacitor 100 nF typical must be connected between BOOT 18 I this pin and SW. Bypass pin for the internal regulator that supplies power to the internal controls of the device. Normal regulation BP3 13 O voltage is 3.3 V. Connect a 100 nF or larger capacitor from this pin to GND. Bypass pin for the internal regulator that supplies power to the gate drivers. Normal regulation voltage is 6.5 V. BP6 14 O Connect a 1- μF or larger capacitor from this pin to GND. CLK 1 I Clock input for the PMBus interface Logic level input that controls the startup and shutdown of the converter, Exact functionality is determined by CNTL 2 I PMBus options. COMP 6 O Output of the error amplifier. Used for control loop compensation. DATA 24 I/O Data I/O for the PMBus interface DIFFO 8 O Output of the unity gain remote voltage sense amplifier. Typically connected to the voltage divider on FB FB 7 I Inverting input to the error amplifier. A voltage divider is connected here to sense the output voltage. Common connection for the device. This pin should connect to the thermal pad under the device package and to the power stage ground, preferably close to the source of the Low-side or rectifier FET. Connections should be GND 15 – arranged so that no power level current slow across the pad connected to the thermal pad on the underside of the device. HDRV 19 O Gate drive signal to the high-side FET ISNS – 11 I Inverting input to the current sense amplifier ISNS+ 12 I Non-inverting input to the current sense amplifier LDRV 16 O Output used to drive the gate of the low-side or rectifier FET. Power good output. This is an open drain output that pulls low when any fault condition exists within the device PGOOD 3 O or when the device is not operating within a user selectable operating range of the nominal output voltage of the converter. 8 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :TPS40400 |
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