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VAR Datasheet(PDF) 3 Page - Vishay Siliconix |
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VAR Datasheet(HTML) 3 Page - Vishay Siliconix |
3 / 5 page FIGURE 2 - STANDARD DIMENSIONS Lead Material #22 AWG Round Solder Coated Copper W L LS H LL Soldered PCB This product is fragile and may be damaged if mishandled. VPG assumes no responsibility for damage caused by improper handling. TABLE 2 - SPECIFICATIONS RESISTANCE RANGE ( Ω) MAXIMUM WORKING VOLTAGE AMBIENT POWER RATING DIMENSIONS at + 70 °C at + 125 °C INCHES mm 10 to 100K 200 0.4 W 0.2 W W: 0.080 max. L: 0.250 max. H: 0.310 max. LL: 1.000 ± 0.125 LS: 0.150 ± 0.005 W: 2.03 max. L: 6.35 max. H: 7.87 max. LL: 25.4 ± 3.18 LS: 3.81 ± 0.13 FIGURE 3 - POWER DERATING CURVE 200 % 175 % 150 % 125 % 100 % 75 % 50 % 25 % 0 - 75 - 50 - 25 0 + 25 + 50 + 75 + 100 + 125 + 150 + 175 + 200 Ambient Temperature (°C) - 55 °C + 70 °C Double Rated Power Rated Power VAR Vishay Foil Resistors Document Number: 63140 For any questions, contact: foil@vishaypg.com www.vishayfoilresistors.com Revision: 22-Nov-10 3 FIGURE 4 - TRIMMING TO VALUES (Conceptual Illustration) Mutual Inductance Reduction due to Opposing Current in Adjacent Lines Current Path Before Trimming Note: Foil shown in black, etched spaces in white Interloop Capacitance Reduction in Series Trimming Process Removes this Material from Shorting Strip Area Changing Current Path and Increasing Resistance Current Path After Trimming To acquire a precision resistance value, the Bulk Metal Foil chip is trimmed by selectively removing built-in “shorting bars.” To increase the resistance in known increments, marked areas are cut, producing progressively smaller increases in resistance. This method reduces the effect of “hot spot” and improves the long term stability of the hybrid chips. |
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