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GS1535ACFUE3 Datasheet(PDF) 7 Page - Gennum Corporation |
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GS1535ACFUE3 Datasheet(HTML) 7 Page - Gennum Corporation |
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7 / 27 page  GS1535A / GS9065A Data Sheet 31497 - 4 June 2006 7 of 27 24, 25, 26 SS[2:0] Bi-directional When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . *Only applies to the GS1535A. For the GS9065A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 27 ASI/177 Logic Input When set HIGH, the device disables the 177Mb/s data rate in the data rate detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI. When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is applied, the device could false lock to the 177MHz signal. 28 LD Output Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 RSVD Reserved Do not connect. 30 VCC_DIG Power Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD Output GS1535A: This signal will be set LOW by the device when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. GS9065A: This signal will go HIGH when the reclocker has locked to the input SD signal. It will be LOW otherwise. 34 KBB Analog Input Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 35, 38 - 42 RSVD Reserved Do not connect. 36 DDO_MUTE Logic Input Mutes the DDO/DDO outputs, when not in bypass mode. Table 1-1: GS1535A / GS9065A Pin Descriptions (Continued) Pin Number Name Type Description SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 0 0 0 143 0 0 1 177 0 1 0 270 0 1 1 360 1 0 0 540 1 0 1 1483.5/1485* |
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