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HMC792LP4E Datasheet(PDF) 5 Page - Hittite Microwave Corporation |
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HMC792LP4E Datasheet(HTML) 5 Page - Hittite Microwave Corporation |
5 / 10 page For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 8 8 - 5 HMC792LP4E v00.0609 0.25 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz PUP Truth Table Power-Up States Control Voltage Input Reference Insertion Loss D5 D4 D3 D2 D1 D0 High High High High High High 0 dB High High High High High Low -0.25 dB High High High High Low High -0.5 dB High High High Low High High -1 dB High High Low High High High -2 dB High Low High High High High -4 dB Low High High High High High -8 dB Low Low Low Low Low Low -15.75 dB Any combination of the above states will provide an attenuation equal to the sum of the bits selected. Truth Table Control Voltage Table Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch Enable) must be at a logic high at all times to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. LE PUP1 PUP2 Relative Attenuation 0 0 0 -15.75 0 1 0 -12 0 0 1 -8 0 1 1 Insertion Loss 1 X X 0 to -15.75 dB Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The attenuator latches in the desired power-up state approximately 200 ms after power-up. Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Parameter Typ. Min. serial period, t SCK 100 ns Control set-up time, t CS 20 ns Control hold-time, t CH 20 ns LE setup-time, t LN 10 ns Min. LE pulse width, t LEW 10 ns Min LE pulse spacing, t LES 630 ns Serial clock hold-time from LE, t CKN 10 ns Hold Time, t PH. 0 ns Latch Enable Minimum Width, t LEN 10 ns Setup Time, t PS 2 ns State Vdd = +3V Vdd = +5V Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA High 2 to 3V @ <1 µA 2 to 5V @ <1 µA |
Similar Part No. - HMC792LP4E_10 |
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Similar Description - HMC792LP4E_10 |
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