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HMC701LP6CE

v07.0411

8 GHz 16-Bit Fractional-n Pll

Sine reference input

the crystal reference sine input stage is shown in Figure 2. this is the lowest noise reference path. this is a common

emitter single ended bipolar buffer. the XSin input pin is Dc coupled and has about 950 mV bias on it. Expected

input is a 0 dBm sinusoid from a 50 ohm source. normally the input should be ac coupled externally. the sine buffer

input impedance is dominated by a 25 ohm shunt resistor in series with a 50 pF on chip cap. Should a lower input

impedance be needed, an external 50 ohm shunt resistor can be used, Dc isolated by an external bypass cap. the

sine input reference path phase noise floor is approximately equivalent to -159 dBc/Hz. For best performance care

should be taken to provide a crystal reference source with equivalent or better phase noise floor.

Figure 2. Ref Sine Input

Square Wave reference input

the square wave ref input stage is shown in Figure 3. the stage is designed to accept square wave inputs from cML

to cMoS levels. Slightly degraded phase noise performance may be obtained with quasi sine 1 Vpp inputs. it may be

necessary to attenuate very large cMoS levels if absolute best in close phase noise performance is required. input

reference should have a noise floor better than -160 dBc/Hz to avoid degradation of the input reference path.

Figure 3. Square Wave Ref Input Stage