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Phone: 978-250-3343

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12

Absolute Maximum Ratings

RF Input Power

20 dBm

RF Output Power

22 dBm

Digital Inputs (B0-B4, Shift Clock,

Latch Enable & Data Input)

-0.5V to Vdd +0.5V

Bias Voltage (Vdd)

5.6 V

Junction Temperature

125 °C

Continuous Pdiss (T = 85 °C)

0.54 W

Thermal Resistance

(Junction to ground paddle)

74.3 °C/W

Storage Temperature

-65 to +150 °C

Operating Temperature

-40 to +85 °C

ELECTROSTATIC SENSITIVE DEVICE

OBSERVE HANDLING PRECAUTIONS

Bias Voltage

Vdd (V)

Idd (Typ.) (mA)

5V

65

PUP Truth Table

LE

PUP1

PUP2

Gain Relative to

Maximum Gain

000

Insertion Loss

010

-8

001

-16

011

-23

1

X

X

0 to -23 dB

Note: Power-Up with LE= 1 provides direct parallel operation with

B4-B0.

Power-Up States

If LE is set to logic LOW at power-up, the logic state of

PUP1 and PUP2 determines the power-up state of the

part per PUP truth table. If the LE is set to logic HIGH

at power-up, the logic state of B4-B0 determines the

power-up state of the part per truth table. The DVGA

latches in the desired power-up state approximately

200 ms after power-up.

Power-On Sequence

The ideal power-up sequence is: GND, Vdd, digital

inputs, RF inputs. The relative order of the digital

inputs are not important as long as they are powered

after Vdd / GND

ATTENUATION

(dB)

B2

B1

B0

0

0

0000

1

0

0001

2

0

0010

3

0

0011

4

0

0100

5

0

0101

6

0

0110

7

0

0111

8

0

1000

9

0

1001

10

01010

11

01011

12

01100

13

01101

14

01110

15

01111

16

1X0

0

0

17

1X0

0

1

18

1X0

1

0

19

1X0

1

1

20

1X1

0

0

21

1X1

0

1

22

1X1

1

0

23

1X1

1

1

[1] Enabling B4 disables B3, the minimum attenuation is 16 dB

Truth Table

HMC628LP4 / 628LP4E

v07.0410

BiCMOS MMIC 5-Bit DIGITAL

VARIABLE GAIN AMPLIFIER, 50 - 800 MHz

Control Voltage Table

State

Vdd = +3V

Vdd = +5V

Low

0 to 0.5V @ <1 μA

0 to 0.8V @ <1 μA

High

2 to 3V @ <1 μA

2 to 5V @ <1 μA