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627LP5E Datasheet(PDF) 6 Page - Hittite Microwave Corporation |
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627LP5E Datasheet(HTML) 6 Page - Hittite Microwave Corporation |
6 / 10 page 12 - 6 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 12 Absolute Maximum Ratings RF Input Power [1] 11.5 dBm (T = +85 °C) Digital Inputs (Reset, Shift Clock, Latch Enable & Serial Input) -0.5V to Vdd +0.5V Bias Voltage (Vdd) 5.6V Collector Bias Voltage (Vcc) 5.5V Channel Temperature 150 °C Continuous Pdiss (T = 85 °C) (derate 9 mW/°C above 85 °C) [1] 0.593 W Thermal Resistance 110 °C/W Storage Temperature -65 to +150 °C Operating Temperature -40 to +85 °C [1] At max gain settling ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS Bias Voltage PUP Truth Table Power-Up States Vdd (V) Idd (Typ.) (mA) +5 2 Vs (V) Is (mA) +5 88 Control Voltage Input Gain Relative to Maximum Gain D5 D4 D3 D2 D1 D0 High High High High High High 0 dB High High High High High Low -0.5 dB High High High High Low High -1 dB High High High Low High High -2 dB High High Low High High High -4 dB High Low High High High High -8 dB Low High High High High High -16 dB Low Low Low Low Low Low -31.5 dB Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Truth Table If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz LE PUP1 PUP2 Gain Relative to Maximum Gain 0 0 0 -31.5 0 1 0 -24 0 0 1 -16 0 1 1 Insertion Loss 1 X X 0 to -31.5 dB Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. Control Voltage Table State Vdd = +3V Vdd = +5V Low 0 to 0.5V @ <1 µA 0 to 0.8V @ <1 µA High 2 to 3V @ <1 µA 2 to 5V @ <1 µA |
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