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ICS9148-08 Datasheet(PDF) 5 Page - Integrated Device Technology

Part # ICS9148-08
Description  Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Download  14 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9148-08 Datasheet(HTML) 5 Page - Integrated Device Technology

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ICS9148-08
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCIActive/Inactive Register(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2.PCICLK5 only in Desktop Mode
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
40
1
CPUCLK3 (Act/Inact)
Bit 2
41
1
CPUCLK2 (Act/Inact)
Bit 1
43
1
CPUCLK1 (Act/Inact)
Bit 0
44
1
CPUCLK0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
7
1
PCICLK_F (Act/Inact)
Bit 5
15
1
PCICLK5 (Act/Inact)
(Desktop only)
Bit 4
14
1
PCICLK4 (Act/Inact)
Bit 3
12
1
PCICLK3 (Act/Inact)
Bit 2
11
1
PCICLK2 (Act/Inact)
Bit 1
10
1
PCICLK1 (Act/Inact)
Bit 0
8
1
PCICLK0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
28
1
SDRAM7 (Act/Inact)
Bit 6
29
1
SDRAM6 (Act/Inact)
Bit 5
31
1
SDRAM5 (Act/Inact)
Bit 4
32
1
SDRAM4 (Act/Inact)
Bit 3
34
1
SDRAM3 (Act/Inact)
Bit 2
35
1
SDRAM2 (Act/Inact)
Bit 1
37
1
SDRAM1 (Act/Inact)
Bit 0
38
1
SDRAM0 (Act/Inact)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching. These outputs are designed to be
configured at power-on and are not expected to be
configured during the normal modes of operation.
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
17
1
SDRAM11 (Act/Inact)
Bit 2
18
1
SDRAM10 (Act/Inact)
Bit 1
20
1
SDRAM9 (Act/Inact)
Bit 0
21
1
SDRAM8 (Act/Inact)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from
switching. These outputs are designed to be configured at
power-on and are not expected to be configured during the
normal modes of operation.
2. REF1 only in Desktop Mode
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
47
1
IOAPIC0 (Act/Inact)
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
46
1
REF1 (Act/Inact)
Bit 0
2
1
REF0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
-
1
(Reserved)
Bit 0
-
1
(Reserved)
Note: PWD = Power-Up Default
Byte 6: Optional Register For Possible Future Requirements
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.


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