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ICS854S202I-01 Datasheet(PDF) 10 Page - Integrated Device Technology |
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ICS854S202I-01 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 17 page  IDT™ / ICS™ LVDS MULTIPLEXER 10 ICS854S202AYI-01 REV. A JANUARY 8, 2007 ICS854S202I-01 12:2, DIFFERENTIAL-LVDS MULTIPLEXER PRELIMINARY INPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k Ω resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVDS OUTPUT All unused LVDS output pairs can be either left floating or ter minated with 100 Ω across. If they are left floating, we recommend that there is no trace attached. APPLICATION INFORMATION Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD = 3.3V, V_REF should be 1.25V V_REF R1 1K C1 0.1u R2 1K Single Ended Clock Input CLKx nCLKx VDD |
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