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MAX11606 Datasheet(PDF) 5 Page - Maxim Integrated Products |
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MAX11606 Datasheet(HTML) 5 Page - Maxim Integrated Products |
5 / 22 page Note 1: All WLP devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design and characterization. Note 2: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at VDD = 5V and the MAX11607/MAX11609/MAX11611 are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs. Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 4: Offset nulled. Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD. Note 8: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.1µF capacitor and a 2k Ω series resistor (see the Typical Operating Circuit). Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVP-P. Note 10: Measured as follows for the MAX11607/MAX11609/MAX11611: and for the MAX11606/MAX11608/MAX11610, where N is the number of bits: Note 11: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s falling edge (see Figure 1). Note 12: The minimum value is specified at TA = +25°C. Note 13: CB = total capacitance of one bus line in pF. Note 14: fSCL must meet the minimum clock low time plus the rise/fall times. VV VV V VV FS FS REF N (. ) ( . ) (. . ) 55 45 21 55 45 − − − []× ⎡ ⎣ ⎢ ⎤ ⎦ ⎥ VV V V V VV FS FS REF N (. ) ( . ) (. . ) 36 27 21 36 27 − − − []× ⎡ ⎣ ⎢ ⎤ ⎦ ⎥ Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages _______________________________________________________________________________________ 5 TIMING CHARACTERISTICS (Figure 1) (continued) (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless other- wise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rise Time of SCL Signal (Current Source Enabled) tRCL Measured from 0.3VDD to 0.7VDD 20 80 ns Rise Time of SCL Signal after Acknowledge Bit tRCL1 Measured from 0.3VDD to 0.7VDD 20 160 ns Fall Time of SCL Signal tFCL Measured from 0.3VDD to 0.7VDD 20 80 ns Rise Time of SDA Signal tRDA Measured from 0.3VDD to 0.7VDD 20 160 ns Fall Time of SDA Signal tFDA Measured from 0.3VDD to 0.7VDD (Note 12) 20 160 ns Setup Time for STOP (P) Condition tSU,STO 160 ns Capacitive Load for Each Bus Line CB 400 pF Pulse Width of Spike Suppressed tSP (Notes 11 and 14) 0 10 ns |
Similar Part No. - MAX11606_11 |
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Similar Description - MAX11606_11 |
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