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MAX6681 Datasheet(PDF) 3 Page - Maxim Integrated Products

Part # MAX6681
Description  ±1°C Fail-Safe Remote/Local Temperature Sensors with SMBus Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX6681 Datasheet(HTML) 3 Page - Maxim Integrated Products

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±1°C Fail-Safe Remote/Local Temperature
Sensors with SMBus Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Typical Operating Circuit, VCC = 3.0V to 5.5V, TA = -25°C to +125°C, unless otherwise specified. Typical values are at VCC
= 3.3V and TA = +25°C.)
Note 1: TA = +25°C to +85°C.
Note 2: If both the local and the remote junction are below TA = -20°C, then VCC > 3.15V.
Note 3: Conversions done in extended mode. For legacy mode, current is approximately half.
Note 4: Timing specifications guaranteed by design.
Note 5: The serial interface resets when SMBCLK or SMBDATA is low for more than tTIMEOUT.
Note 6: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SMBCLK’s falling edge.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CRIT0, CRIT1, ADD0, ADD1, RESET, INT_SEL, SENS_SEL
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
ILEAK
-1
+1
µA
(
ALERT, OVERT)
Output Low Sink Current
VOL = 0.4V
1
mA
Output High Leakage Current
VOH = 5.5V
1
µA
SMBus INTERFACE (SMBCLK, SMBDATA,
STBY)
Logic Input Low Voltage
VIL
0.8
V
VCC = 3.0V
2.2
Logic Input High Voltage
VIH
VCC = 5.5V
2.4
V
Input Leakage Current
ILEAK
VIN = GND or VCC
±2
µA
Output Low Sink Current
IOL
VOL = 0.6V
6
mA
Input Capacitance
CIN
5pF
SMBus-COMPATIBLE TIMING (Note 5)
Serial Clock Frequency (Note 5)
fSCL
100
kHz
Bus Free Time Between STOP
and START Condition
tBUF
4.7
µs
START Condition Setup Time
4.7
µs
Repeat START Condition Setup
Time
tSU:STA
90% to 90%
50
ns
START Condition Hold Time
tHD:STA
10% of SMBDATA to 90% of SMBCLK
4
µs
STOP Condition Setup Time
tSU:STO
90% of SMDCLK to 90% of SMBDATA
4
µs
Clock Low Period
tLOW
10% to 10%
4.7
µs
Clock High Period
tHIGH
90% to 90%
4
µs
Data Setup Time (Note 6)
tHD:DAT
250
ns
Receive SCL/SDA Rise Time
tR
1µs
Receive SCL/SDA Fall Time
tF
300
ns
Pulse Width of Spike Suppressed
tSP
050
ns
SMBus Timeout (Note 5)
SMBDATA low period for interface reset
25
37
45
ms


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