10-Bit, Dual, Nonvolatile, Linear-Taper

Digital Potentiometers

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5

TIMING CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

ANALOG SECTION

MAX5494/MAX5498

5

Wiper Settling Time (Note 6)

MAX5495/MAX5499

22

µs

SPI-COMPATIBLE SERIAL INTERFACE (Figure 6)

SCLK Frequency

7

MHz

SCLK Clock Period

140

ns

SCLK Pulse-Width High

60

ns

SCLK Pulse-Width Low

60

ns

CS Fall to SCLK Rise Setup

60

ns

SCLK Rise to CS Rise Hold

0ns

DIN to SCLK Setup

40

ns

DIN Hold After SCLK

0ns

SCLK Rise to CS Fall Delay

15

ns

CS Rise to SCLK Rise Hold

60

ns

CS Pulse-Width High

150

ns

Write NV Register Busy Time

12

ms

and measured with a high-input-impedance voltmeter.

Note 4: The wiper resistance is measured using the source currents given in Note 3.

0.5V). See the Supply Current vs. Digital Input Voltage graph in the

Typical Operating Characteristics.

Note 6: Wiper settling test condition uses the voltage-divider with a 10pF load on W_. Transition code from 0 to 495 and measure

the time from CS going high to the wiper voltage settling to within 0.5% of its final value.