MAX3396EETP+ datasheet(7/20 Pages) MAXIM

Part #	MAX3396EETP+

Description	±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/ Octal-Level Translators with Speed-Up Circuitry

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Manufacturer	MAXIM [Maxim Integrated Products]

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Detailed Description

The MAX3394E/MAX3395E/MAX3396E bidirectional

level translators provide level shifting required for data

transfer in a multivoltage system. Internal slew-rate

enhancement circuitry features 10mA current-sink and

15mA current-source drivers to isolate capacitive loads

from lower current drivers. In open-drain systems, slew-

rate enhancement enables fast data rates with larger

pullup resistors and increased bus load capacitance.

Externally applied voltages, VCC and VL, set the logic-

high levels for the device. A logic-low signal on one I/O

side of the device appears as a logic-low signal on the

opposite I/O side and vice-versa. Each I/O line is pulled

up to VCC or VL by an internal pullup resistor, allowing

the devices to be driven by either push-pull or open-

drain drivers.

±15kV ESD-Protected, High-Drive Current, Dual-/Quad-/

Octal-Level Translators with Speed-Up Circuitry

_______________________________________________________________________________________

7

Pin Description

MAX3394E

MAX3395E

MAX3396E

TDFN

UCSP

TQFN

UCSP

TQFN

UCSP

NAME

FUNCTION

1

A1

11B1

14D3

VCC

VCC Supply Voltage +1.65V

≤ VCC ≤ +5.5V. Bypass

VCC to GND with a 0.1µF ceramic capacitor and a

1µF or greater ceramic capacitor as close to the

device as possible.

2

B1

6

B3

4

A4

EN

Enable Input. Drive EN logic high for normal

operation. Drive EN logic low to force all I/O lines to

a high-impedance state and disconnect internal

pullup resistors.

3

A2

10

C1

18

C1

I/O VCC1

I/O 1 Referred to VCC

4

A3

9

C2

16

D1

I/O VCC2

I/O 2 Referred to VCC

5

B3

5

B4

13

D4

GND

Ground

6

C3

2

A2

20

A1

I/O VL2

I/O 2 Referred to VL

7

C2

1

A1

19

B1

I/O VL1

I/O 1 Referred to VL

8

C1

12

B2

3

A3

VL

Logic Supply Voltage +1.2V

≤ VL ≤ VCC. Bypass VL

to GND with a 0.1µF or greater ceramic capacitor

as close to the device as possible.

—

3

A3

1

B2

I/O VL3

I/O 3 Referred to VL

—

4

A4

2

A2

I/O VL4

I/O 4 Referred to VL

—

7

C4

15

D2

I/O VCC4

I/O 4 Referred to VCC

—

8

C3

17

C2

I/O VCC3

I/O 3 Referred to VCC

—

12

C3

I/O VCC5

I/O 5 Referred to VCC

—

11

D5

I/O VCC6

I/O 6 Referred to VCC

—

10

C4

I/O VCC7

I/O 7 Referred to VCC

—

9

C5

I/O VCC8

I/O 8 Referred to VCC

—

5

B3

I/O VL5

I/O 5 Referred to VL

—

6

A5

I/O VL6

I/O 6 Referred to VL

—

7

B4

I/O VL7

I/O 7 Referred to VL

—

8

B5

I/O VL8

I/O 8 Referred to VL

EP

—

EP

—

EP

—

EP

Exposed Pad. Connect exposed pad to GND.

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MAX3396EETP+ Datasheet(PDF) 7 Page - Maxim Integrated Products

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