16-Bit, +5V, 200ksps ADC with 10µA

Shutdown

10

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Digital Interface

Initialization after Power-Up and

Starting a Conversion

The digital interface consists of two inputs, SCLK and

CS, and one output, DOUT. A logic high on CS places

the MAX1162 in shutdown (AutoShutdown) and places

DOUT in a high-impedance state. A logic low on CS

places the MAX1162 in the fully powered mode.

To start a conversion, pull CS low. A falling edge on CS

initiates an acquisition. SCLK drives the A/D conversion

and shifts out the conversion results (MSB first) at DOUT.

Timing and Control

Conversion-start and data-read operations are con-

trolled by the CS and SCLK digital inputs (Figures 6

and 7). Ensure that the duty cycle on SCLK is between

40% and 60% at 4.8MHz (the maximum clock frequen-

cy). For lower clock frequencies, ensure that the mini-

mum high and low times are at least 65ns.

Conversions with SCLK rates less than 100kHz can

result in reduced accuracy due to leakage.

Note: Coupling between SCLK and the analog

inputs (AIN and REF) may result in an offset.

Variations in frequency, duty cycle, or other aspects

of the clock signal’s shape result in changing offset.

A CS falling edge initiates an acquisition sequence.

The analog input is stored in the capacitive DAC,

DOUT changes from high impedance to logic low, and

the ADC begins to convert after the sixth clock cycle.

SCLK drives the conversion process and shifts out the

conversion result on DOUT.

SCLK begins shifting out the data (MSB first) after the

falling edge of the 8th SCLK pulse. Twenty-four falling

clock edges are needed to shift out the eight leading

zeros and 16 data bits. Extra clock pulses occurring

after the conversion result has been clocked out, and

prior to the rising edge of CS, produce trailing zeros at

DOUT and have no effect on the converter operation.

Force CS high after reading the conversion’s LSB to

reset the internal registers and place the MAX1162 in

shutdown. For maximum throughput, force CS low

again to initiate the next conversion immediately after

Note: Forcing

CS high in the middle of a conversion

immediately aborts the conversion and places the

MAX1162 in shutdown.

800

Ω

HOLD

HOLD

3pF

AIN

REF

GND

ZERO

CAPACITIVE DAC

AUTO-ZERO

RAIL

TRACK

TRACK

Figure 5. Equivalent Input Circuit

CS

SCLK

20

16

24

12

14

8

6

DOUT

D15

D14

D13

D12

D11

D10

D9

D1

D0

D8

D5

D4

D3

D2

D7

D6

Figure 6. External Timing Diagram