ISL97687

3

FN7714.0

September 15, 2011

Pin Configurations

ISL97687

(28 LD 5x5 TQFN)

TOP VIEW

ISL97687

(28 LD SOIC)

TOP VIEW

PWMI

STV

EN_ADIM

EN_PS

VLOGIC

EN_VSYNC

VDC

ACTL

OSC

ISET2

ISET1

COMP

OVP

1

2

3

4

5

6

7

21

20

19

18

17

16

8

910

11

12

13

THERMAL*

PAD

PWM_SET/PLL

15

14

28

27

26

25

24

23

22

*EXPOSED THERMAL PAD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CH2

EN_ADIM

EN_PS

VLOGIC

ISET2

ISET1

CH1

PGND

CSEL

PWMI

STV

EN_VSYNC

VDC

VIN

EN

AGND

GD

SLEW

CS

PGND

PWM_SET/PLL

OVP

COMP

OSC

ACTL

PGND

CH4

CH3

Pin Descriptions

TQFN

SOIC

PIN NAME PIN TYPE

PIN DESCRIPTION

1

5

PWMI

I

PWM Brightness Control Input pin

2

6

STV

I

Start Vertical Frame signal, used in VSYNC mode

3

7

EN_ADIM

I

Enable Analog Dimming

4

8

EN_PS

I

Enable Phase Shift

5

9

VLOGIC

S

Internal 2.5V Digital Bias Regulator. Needs Decoupling Capacitor added to ground

6

10

EN_VSYNC

I

needs to be configured with an RC network. Pin can be tied to VDC or VLOGIC to enable function

7

11

VDC

S

Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor added ground

8

12

VIN

S

Main Power Input. Range: 9V to 32V

9

13

EN

I

LED Driver Enable. Whole chip will shut down when low

10

14

AGND

S

Analog Ground

11

15

GD

O

External Boost FET gate control

12

16

SLEW

I

Boost Regulation Switching Slew Rate control

13

17

CS

I

External Boost FET current sense input

14

18

PGND

S

Boost FET gate driver power ground and ground reference for CS pin

15

19

PWM_SET/

PLL

I

For direct PWM mode, tie this pin high to VDC. For other non-VSYNC modes, connect to a resistor

to set the dimming frequency. If the VSYNC function is enabled, connect this pin to the PLL loop

filter network.

16

20

OVP

I

Overvoltage Protection Input as well as Output Voltage feedback pin

17

21

COMP

I

Boost compensation