ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

10

FN7662.0

September 15, 2011

Functional Overview

The ISL705xRH and ISL706xRH provide the functions needed for

monitoring critical voltages in high reliability applications such as

microprocessor systems. Functions of the these supervisors include

power-on reset control; supply voltage supervisions; power-fail

detection; manual-reset assertion and a watch dog timer. The

integration of all these functions along with their high threshold

accuracy, low power consumption, and radiation tolerance make

these devices ideal for critical supply monitoring.

Reset Output

Reset control has long been a critical aspect of embedded

control design. Microprocessors require a reset signal during

power up to ensure that the system environment is stable before

initialization.

The reset signal provides several benefits:

• It prevents the system microprocessor from starting to operate

with insufficient voltage.

• It prevents the processor from operating prior to stabilization

of the oscillator.

• It ensures that the monitored device is held out of operation

until internal registers are initialized.

• It allows time for an FPGA to perform its self configuration

prior to initialization of the circuit.

Figure 3). If a brownout condition occurs in the middle of a

previously initiated reset pulse, the pulse is lengthened 200ms

(typ).

The ISL705BRH and ISL706BRH active-high RST output is simply

the complement of the RST output, and is guaranteed to be valid

active-low open-drain reset output is functionally identical to RST.

Power Failure Monitor

Power-Failure Monitor feature that supervises an additional

critical voltage on the Power-Fail Input (PFI) pin. For example, the

PFI pin could be used to provide an early power-fail warning,

The threshold detector can be adjusted using an external resistor

divider network to provide custom voltage monitoring for

Figure 14).

Manual Reset

The manual reset input (MR) allows designers to add manual

system reset capability via a push button switch (see Figure 15).

The MR input is an active low debounced input which asserts

150ns. After MR is released, the reset output remains asserted

so it can be driven by external logic. By connecting WDO to MR,

one can force a watchdog time out to generate a reset pulse.

Watch Dog Timer

The watchdog time circuit checks for coherent program

execution by monitoring the WDI pin. If the processor does not

low. As long as reset is asserted or the WDI pin is tri-stated, the

watchdog timer will stay cleared and not count. As soon as reset

is released and WDI is driven high or low, the timer will start

counting. Pulses as short as 50ns can be detected on the

ISL705xRH, on ISL706xRH pulses as short as 100ns can be

detected.

Unlike the reset outputs, however, WDO goes high as soon as

open or connected to a tri-stated high impedance input, the

Applications Information

Negative Voltage Sensing

This family of devices can be used to sense and monitor the

monitors the positive supply while PFI monitors the negative rail.

As the differential voltage across the R1, R2 divider is increased,

the resistor values must be chosen such that the PFI node is

<1.25V when the -V supply is satisfactory and the positive supply

VIN

R1 R2

+

R2

----------------------

⎝⎠

⎛⎞

=

(EQ. 1)

PFI

ISL705xRH/ISL706xRH

MR

PB

20k

FIGURE 15. CONNECTING A MANUAL RESET PUSH-BUTTON

ISL705xRH/ISL706xRH