MOSA

MS6260

Gain And Attenuation Volume Controller IC

REV 3

6

www.mosanalog.com

Acknowledge

During the Acknowledge clock pulse, the master (up) put a resistive HIGH level on the SDA line. The peripheral

(audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge clock pulse so that

the SDA line is in a stable LOW state during this clock pulse. Please refer to the diagram below.

SCL

SDA

MSB

Acknowledge

12

3

7

8

9

Start

The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise,

the SDA line will remain at the HIGH level during the ninth (9

generate the STOP information in order to abort the transfer.

Timing of SDA and SCL bus lines

S

S

P

SDA

SCL

Standard mode

Symbol

Parameter

Min

Max

Unit

SCL clock frequency

0

100

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is generated

4.0

-

us

LOW period of the SCL clock

4.7

-

us

HIGH period of the SCL clock

4.0

-

us

Set-up time for a repeated START condition

4.7

-

us

Data hold time:

For I

0

3.45

us

Data-set-up time

250

-

ns

Rise time of both SDA and SCL signals

-

1000

ns

Fall time of both SDA and SCL signals

-

300

ns

Set-up time for STOP condition

4.0

-

us

Bus free time between a STOP and START condition

4.7

-

us

Capacitive load for each bus line

-

400

pF

Noise margin at the LOW level for each connected device (including

hysteresis)

-

V

Noise margin at the HIGH level for each connected device (including

hysteresis)

-

V