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ISL80101-ADJ Datasheet(PDF) 3 Page - Intersil Corporation

Part # ISL80101-ADJ
Description  High Performance 1A LDO
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL80101-ADJ Datasheet(HTML) 3 Page - Intersil Corporation

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ISL80101
3
FN6931.1
August 31, 2011
Pin Configurations
ISL80101
(10 LD 3X3 DFN)
TOP VIEW
2
3
4
1
5
9
8
7
10
6
VOUT
VOUT
SENSE
PG
GND
VIN
VIN
NC
ENABLE
SS
EPAD
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VOUT
Regulated output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External
Capacitor Requirements” on page 8 for more details.
3
SENSE
The PGOOD circuit uses this input to monitor the output voltage status, providing a remote voltage sense.
4
PG
This is an open drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not
in regulation. This pin must be grounded if not used.
5GND
Ground.
6
SS
External capacitor on this pin adjusts startup ramp and controls inrush current.
7ENABLE
VIN independent chip enable. TTL and CMOS compatible.
8
NC
No connection. Leave floating.
9, 10
VIN
Input supply. A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External
Capacitor Requirements” on page 8 for more details.
-
EPAD
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.


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