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74LVC2G125GS Datasheet(PDF) 4 Page - NXP Semiconductors |
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74LVC2G125GS Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 22 page 74LVC2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 11 — 9 September 2010 4 of 22 NXP Semiconductors 74LVC2G125 Dual bus buffer/line driver; 3-state 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Fig 5. Pin configuration SOT996-2 Fig 6. Pin configuration SOT902-1 001aai243 74LVC2G125 Transparent top view 8 7 6 5 1 2 3 4 1OE 1A 2Y GND VCC 2OE 1Y 2A 001aae010 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G125 Table 3. Pin description Symbol Pin Description SOT505-2, SOT765-1, SOT833-1, SOT1089, SOT996-2, SOT1116 and SOT1203 SOT902-1 1OE, 2OE 1, 7 7, 1 output enable input (active LOW) 1A, 2A 2, 5 6, 3 data input GND 4 4 ground (0 V) 1Y, 2Y 6, 3 2, 5 data output VCC 8 8 supply voltage Table 4. Function table[1] Control Input Output nOE nA nY LLL LH H HX Z |
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