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ACT4050YH-T Datasheet(PDF) 2 Page - Active-Semi, Inc |
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ACT4050YH-T Datasheet(HTML) 2 Page - Active-Semi, Inc |
2 / 13 page Active-Semi ACT4050 Rev 2, 01-Jul-11 - 2 - www.active-semi.com Copyright © 2011 Active-Semi, Inc. Innovative Power TM ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE PINS PACKING ACT4050YH -40°C to 85°C SOP-8/EP 8 TUBE ACT4050YH-T -40°C to 85°C SOP-8/EP 8 TAPE & REEL PIN CONFIGURATION PIN DESCRIPTIONS PIN NAME DESCRIPTION 1 BS Bootstrap. This pin acts as the positive rail for the high-side switch’s gate driver. Connect a 10nF capacitor between BS and SW. 2 IN Input Supply. Bypass this pin to GND with a low ESR capacitor. See Input Capacitor in the Application Information section. 3 SW Switch Output. Connect this pin to the switching end of the inductor. 4 GND Ground. 5 FB Feedback Input. The voltage at this pin is regulated to 0.817V. Connect to the resistor divider between output and ground to set output voltage. 6 COMP Compensation Pin. See Stability Compensation in the Application Information section. 7 EN Enable Input. When higher than 1.3V, this pin turns the IC on. When lower than 0.9V, this pin turns the IC off. Output voltage is discharged when the IC is off. When left unconnected, EN is pulled up to 4.5V typical with a 2µA pull-up current. 8 N/C Not Connected. EP EP Exposed Pad shown as dashed box. The exposed thermal pad should be connected to board ground plane and pin 4. The ground plane should include a large exposed copper pad under the package for thermal dissipation (see package outline). The leads and exposed pad should be flush with the board, without offset from the board surface. SOP-8/EP |
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