LH543620 datasheet(10/38 Pages) SHARP

Part #	LH543620

Description	1024 x 36 Synchronous FIFO

Download	38 Pages

Scroll/Zoom	100%

Manufacturer	SHARP [Sharp Corporation]

Direct Link	http://sharp-world.com/

Logo

10 / 38 page

Table 1. Input-Port Address

ADI2

ADI1

ADI0

SELECTION

DEFAULT VALUE

(of the selected

REGISTER)

L

RBASE register

0

LL

H

ROFFSET

register

0

LH

L

AF offset value

8

L

H

Parity register

0

HL

L

AE offset value

8

HL

HControl register

1

H

L

Mailbox

0

HH

H

Resource

registers write

disabled

Table 2. Input-Port Word-Width Selection

WSI1

WSI0

FUNCTION

LL

9-Bit Data-Path

Width

Input data D[8:0]

LH

18-Bit Data-Path

Width

Input data D[17:0]

HL

Reserved

HH

36-Bit Data-Path

Width

Input data D[35:0]

PIN NAME

DESCRIPTION

ASYNCHRONOUS CONTROL

RS

Master Reset. When asserted LOW, the LH543620 internal resource registers are set to their

default value. See Table 1. The status flags indicate Empty FIFO.

OE

Output Enable. When asserted LOW, OE forces Q[35:0] to be active. When deasserted HIGH, OE

forces Q[35:0] into a Hi-Z state. Bit 6 of the control register governs whether OE suppresses the

advancement of the Read Pointer (RP). In this case, OE must obey setup time and hold time

relative to CKO.

BYE

Data-Bypass Enable. When asserted LOW, BYE connects Q[35:0] directly to D[35:0].

CAPR

Command-Address Port Reference. CAPR determines the source of the 16-bit word to be loaded

into the resource register. Whenever CAPR is LOW, the word comes from the Input Port. Whenever

CAPR is HIGH (OE is HIGH), the word comes from the Output Port.

NOTES:

1. The destination of the resource register is always the Output Port.

2. CAPR is assumed to be a steady signal. It is not allowed to change ‘on-the-fly’ during operation.

CONTROL SIGNALS SYNCHRONOUS TO THE INPUT CLOCK

ENI1, ENI2

Input-Port Enables. ENI1 and ENI2 are active HIGH and synchronous to the rising edge of CKI.

Data is written into the FIFO memory array when both ENI1 and ENI2 are asserted HIGH.

NOTE: ENI1, ENI2 DO NOT ENABLE writing data into the Resource Registers or the Mailbox.

ADI[2:0]

Input-Port Address. ADI[2:0] specifies the Input-Port destination. See Table 1. ADI[2:0] is

synchronized to the rising edge of CKI.

WSI[1:0]

Input-Port Word-Width Selection. WSI[1:0] selects the Input-Port Word-Width. See Table 2.

WSI[1:0] is synchronous to the rising edge of CKI.

LH543620

1024

× 36 Synchronous FIFO

10

Similar Part No. - LH543620

Manufacturer	Part #	Datasheet	Description
Sharp Corporation	LH543621	475Kb / 57P	512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO

More results

Similar Description - LH543620

Manufacturer	Part #	Datasheet	Description
Sharp Corporation	LH543611	475Kb / 57P	512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO
	LH540215	423Kb / 48P	512 x 18 / 1024 x 18 Synchronous FIFO
	LH540202	156Kb / 18P	CMOS 1024 x 9 Asynchronous FIFO
Integrated Device Techn...	IDT723631	269Kb / 23P	CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36
Integrated Device Techn...	IDT72511	434Kb / 28P	PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
Sharp Corporation	LH5420	2Mb / 35P	256 x 36 x 2 Bidirectional FIFO
Sharp Corporation	LH543601	360Kb / 43P	256 x 36 x 2 Bidirectional FIFO
Integrated Device Techn...	IDT723622	294Kb / 26P	CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
Renesas Technology Corp	IDT72V3640	493Kb / 47P	3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 AUGUST 2018
Integrated Device Techn...	IDT72510	440Kb / 32P	BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT . 1024 x 9-BIT 1024 x 18-BIT . 2048 x 9-BIT

More results

LH543620 Datasheet(PDF) 10 Page - Sharp Corporation

LH543620 Datasheet(HTML) 10 Page - Sharp Corporation

Similar Part No. - LH543620

Similar Description - LH543620

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL