LH543620 datasheet(1/38 Pages) SHARP

Part #	LH543620

Description	1024 x 36 Synchronous FIFO

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Manufacturer	SHARP [Sharp Corporation]

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LH543620

1024

× 36 Synchronous FIFO

FEATURES

•• Fast Cycle Times: 20/25/30 ns

•• Selectable 36/18/9-Bit Word Width for Both

Input Port and Output Port

•• Byte-Order-Reversal Function (i.e.,

‘Big-Endian’ £ ‘Little-Endian’ Conversion)

•• 16-mA-IOL Three-State Outputs

•• Automatic Byte Parity Checking

•• Selectable Byte Parity Generation

•• Five Status Flags: Full, Almost-Full,

Half-Full, Almost-Empty, and Empty

•• All FIFO Status Flags are Synchronous

(AE, HF, AF Through Programming of

Control Register)

•• Programmed Values may be entered from

either Port

•• Two Enable Control Signals for each Port

•• Mailbox Register with Synchronized Flags

•• Asynchronous Data-Bypass Function

•• ‘Smart’ Data-Retransmit Function

•• Configurable for Paralleled FIFO Operation

(72-Bit Data Width)

•• Space-Saving PQFP and TQFP 1

Packages

•• PQFP-to-PGA Package Conversion 2

FUNCTIONAL DESCRIPTION

The LH543620 is a FIFO (First-In, First-Out) memory

device, based on fully-static CMOS RAM technology,

capable of containing up to 1024 36-bit words. It can

replace four or more nine-bit-wide FIFOs in many appli-

cations.

The input port and the output port operate inde-

pendently of each other. Write operations are performed

on the rising edge of the input clock CKI, and enabled by

two enabled signals ENI1, ENI2. Read operations are

performed on the rising edge of the output clock CKO and

enabled by two enabled signals ENO1, ENO2.

Five status flags are available to monitor the memory

array status: Full, Almost-Full, Half-Full, Almost-Empty,

and Empty. The Almost-Full and Almost-Empty flags are

initialized to a default offset of eight locations from their

respective boundaries, but they are each programmable

over the entire FIFO depth.

Both the input port and the output port may be set

independently to operate at three data-word widths: 36

bits, 18 bits, or 9 bits. This setting may be changed during

system operation. The LH543620 can perform Byte-Or-

der-Reversal on the four nine-bit bytes of each 36-bit data

word passing through it, thus accomplishing ‘Big Endian’

↔ ‘Little Endian’ conversion.

When data is read out of the FIFO a byte-parity check

is performed. The parity flag is used to indicate that a

parity error was detected in one of the 9-bit bytes of the

output word.

Parity generation, when selected, creates the parity bit

of each 8-bit byte of the input word. The result is written

into the MSB-bit of each 9-bit byte, overwriting the pre-

vious contents of the bit. The default is odd parity. How-

ever, the FIFO may be programmed to use even parity.

The LH543620 has a data-bypass mode that connects

the output port to the input port asynchronously. A mailbox

facility with Synchronized Flags is provided from the input

port to the output port.

The LH543620’s ‘Smart-Retransmit’ capability sets the

internal-memory read pointer to any arbitrary memory

location. The ‘Smart-Retransmit’ capability includes a

Marking Function and a Programmable Offset to support

data communication and digital signal processing appli-

cations.

1.

This is a final data sheet; except that all references to the TQFP

package have Preliminary status.

2.

For PQFP-to-PGA conversion for thru-hole board designs, Sharp

recommends ITT Pomona Electronics’ SMT/PGA Generic Con-

verter model #5853®. This converter maps the LH543620 132-

pin PQFP to a generic 13

× 13, 132-pin PGA (100-mil pitch). For

more information, contact Sharp or ITT Pomona Electronics at

1500 East Ninth Street, Pomona, CA 91766, (909) 469-2900.

1

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