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LH52256C Datasheet(PDF) 5 Page - Sharp Electrionic Components

Part No. LH52256C
Description  CMOS 256K (32K x 8) Static RAM
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Maker  SHARP [Sharp Electrionic Components]
Homepage  http://sharp-world.com/
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 5 page
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WRITE CYCLE (TA = 0°C to +70°C, VCC = 4.5 V to 5.5 V)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Write cycle time
tWC
70
ns
CE Low to end of write
tCW
45
ns
Address valid to end of write
tAW
45
ns
Address setup time
tAS
0
ns
Write pulse width
tWP
35
ns
Write recovery time
tWR
0
ns
Input data setup time
tDW
30
ns
Input data hold time
tDH
0
ns
WE High to output active
tOW
5
ns
1
WE Low to output in High
impedance
tWZ
030
ns
1
OE High to output in High
impedance
tOHZ
030
ns
1
NOTE:
1.
Active output to high-impedance and high-impedance to output active tests specified for a
±200 mV
transition from steady state levels into the test load.
CAPACITANCE (TA = 25°C, f = 1MHz)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Input capacitance
CIN
VIN = 0 V

7pF
1
I/O capacitance
CI/O
VI/O = 0 V

10
pF
1
NOTE:
1.
This parameter is sampled and not production tested.
DATA RETENTION CHARACTERISTICS (TA = 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Data retention supply voltage
VCCDR
CE
≥ VCCDR – 0.2 V
2.0
5.5
V
Data retention supply current
ICCDR
VCCDR = 3.0 V
CE
≥ VCCDR – 0.2 V
TA = 25
°C
0.3
1.0
µA
TA = 40
°C

3.0
15
Chip enable setup time
tCDR
0

ns
Chip enable hold time
tR
tRC

ns
1
NOTE:
1.
tRC = Read cycle time.
2.
Typical values at TA = 25°C
CMOS 256K (32K
× 8) Static RAM
LH52256C/CH
5




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