LH28F008SA

8M (1M × 8) Flash Memory

4

PIN DESCRIPTION

SYMBOL

TYPE

NAME AND FUNCTION

A

INPUT

ADDRESS INPUTS:

For memory addresses. Addresses are internally latched during

a write cycle.

DQ

INPUT/OUTPUT

DATA INPUT/OUTPUTS:

Inputs data and commands during Command User Interface

write cycles; outputs data during memory array. Status Register and Identifier read

cycles. The data pins are active high and float to tri-state off when the chip is deselected

or the outputs are disabled. Data is internally latched during a write cycle.

CE

»

INPUT

CHIP ENABLE:

Activates the device’s control logic input buffers, decoders, and

sense amplifiers. CE

reduces power consumption to standby levels.

PWD

INPUT

POWERDOWN:

Puts the device in deep powerdown mode. PWD is active low; PWD

high gates normal operation. PWD also locks out block erase or byte write

operations when active low, providing data protection during power transitions.

OE

»

INPUT

OUTPUT ENABLE:

Gates the device’s outputs through the data buffers during a

read cycle. OE

WE

INPUT

WRITE ENABLE:

Controls writes to the Command User Interface and array blocks.

WE is active low. Addresses and data are latched on the rising edge of the

WE Pulse.

RY

OUTPUT

READY/BUSY

: Indicates the status of the internal Write State Machine. When low, it

indicates that the WSM is performing a block erase or byte write operation. RY

high indicates that the WSM is ready for new commands, block erase is suspended or

the device is in deep powerdown mode. RY

to tri-state off when the chip is deselected or data outputs are disabled.

V

PP

SUPPLY

BLOCK ERASE/BYTE WRITE POWER SUPPLY:

for erasing blocks of the array or

writing bytes of each block.

NOTE:

With V

V

CC

DEVICE POWER SUPPLY:

(5 V ±10%, 5 V ±5%)

GND

SUPPLY

GROUND