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BU97930KV-E2 Datasheet(PDF) 9 Page - Rohm |
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BU97930KV-E2 Datasheet(HTML) 9 Page - Rohm |
9 / 24 page Technical Note 9/23 BU97930MUV,BU97931FV,BU9798KV,BU9798GUW,BU97500KV www.rohm.com 2010.04 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. Integrated Regulator Characteristics (Ta=-30 ~ 75°C, VDD=1.8V ~ 3.6V, VLCD=3.3V ~ 5.5V, VSS=0) (BU9798KV) Parameter Symbol Limits Unit Conditions MIN TYP MAX Output voltage 1 Vreg1 4.35 4.5 4.65 V 4.5V setting (VLCD=5.5V, Ta=-30 ~ 75°C) Output voltage 2 Vreg2 4.42 4.5 4.58 V 4.5V setting (VLCD=5.5V, Ta=25°C) Load regulation (**) delta Vreg - - 0.3 V Iout = -300µA (BU9798GUW) Parameter Symbol Limits Unit Conditions MIN TYP MAX Output voltage 1 Vreg1 4.25 4.5 4.70 V 4.5V setting (VLCD=5.5V, Ta=-30 ~ 75°C) Output voltage 2 Vreg2 4.38 4.5 4.62 V 4.5V setting (VLCD=5.5V, Ta=25°C) Load regulation (**) delta Vreg - - 0.3 V Iout = -300µA * In case integrated regulator using, please satisfy condition that Vreg output lower than VLCD – 0.5V. (**) Load regulation: Vreg block load regulation only. Do not include other block ability. Oscillation Frequency Characteristics (Ta=-30 ~ 75°C, VDD=1.8V ~ 3.6V, VLCD=3.3V ~ 5.5V, VSS=0) Parameter Symbol Limits Unit Conditions MIN TYP MAX Frame frequency 1 fFR1 57.6 64 70.4 Hz VDD=3.3V, Ta=25°C, fFR=64Hz setting Frame frequency 2 fFR2 51.2 64 73.0 Hz VDD=2.5 ~ 3.6V fFR=64Hz setting Frame frequency 3 fFR3 45.0 - 64 Hz VDD=1.8 ~ 2.5V fFR=64Hz setting CLKIN Input frequency fCLK - 2 4 MHz MPU interface Characteristics (Ta=-30 ~ 75°C, VDD=1.8V ~ 3.6V, VLCD=3.3V ~ 5.5V, VSS=0) Parameter Symbol Limits Unit Conditions MIN TYP MAX Input rise time tr - - 50 ns Input fall time tf - - 50 ns SCL cycle time tSCYC 250 - - ns “H” SCL pulse width tSHW 50 - - ns “L” SCL pulse width tSLW 50 - - ns SD setup time tSDS 50 - - ns SD hold time tSDH 50 - - ns CSB setup time tCSS 50 - - ns CSB hold time tCSH 50 - - ns “H” CSB pulse width tCHW 50 - - ns Fig.3 Serial Interface Timing CSB SCL SD tCSH tSCYC tSLW tSHW tSDS tSDH tf tr tCSS tCHW |
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