BU9891GUL-W

10/17

www.rohm.com

2010.07 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

Technical Note

●

Application

1) Method to cancel each command

○

READ

○

WRITE

2) At standby

○

Standby current

When CS is “L”, SK input is “L”, DI input is “H”, and even with middle electric potential, current does not increase.

○

Timing

As shown in Fig.38, when SK at standby is “H”, if CS is started, DI status may be read at the rise edge.

At standby and at power ON/OFF, when to start CS, set SK input or DI input to “L” status.

Fig.36 READ cancel available timing

Note 1) If Vcc is made OFF in this area, designated address data is

not guaranteed, therefore write once again.

Note 2) If CS is started at the same timing as that of the SK rise,

write execution/cancel becomes unstable, therefore, it is

recommended to fail in SK=”L” area.

As for SK rise, necessary timing of tCSS/tCSH or higher.

Fig.37 WRITE cancel available timing

Start bit

Ope code

Address

Data

1bit

2bit

8bit

16bit

Cancel is available in all areas in read mode.

・

Method to cancel：cancel by CS=“L”

Start bit

Ope code

Address

Data

tE/W

a

*1

1bit

2bit

8bit

16bit

b

a：From start bit to 27 clock rise

＊1

Cancel by CS=“L”

b：27 clock rise and after

＊1

Cancellation is not available by any means. If Vcc is made OFF in this area,

designated address data is not guaranteed, therefore write once again.

And when SK clock is input continuously, cancellation is not available.

CS

SK

DI

Start bit input

CS=SK=DI=”H”

Wrong recognition as a start bit

CS

SK

DI

Start bit input

If CS is started when SK=”L” or DI=”L”, a start

bit is recognized correctly.

Fig.38 Wrong action timing

Fig.39 Normal action timing

SK

・

D1

Enlarged figure

D0

DI

26

27