Technical Note

10/18

BU9847GUL-W

www.rohm.com

2010.09 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

●

Command

○

Read cycle

Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.

Random read cycle is a command to read data by designating address, and is used generally.

Current read cycle is a command to read data of internal address register without designating address, and is used when

to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data next

address data can be read in succession.

・

In random read cycle, data of designated word address can be read.

・

When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output.

・

When ACK signal “LOW” after D0 is detected, and stop condition is not sent from the master (μ-COM) side, the next

address data can be read in succession.

・

Read cycle is ended by stop condition where “H” is input to ACK signal after D0 and SDA signal is started at

SCL signal “H”.

・

When “H” is not input to ACK signal after D0, sequential read gets in, and the next data is output.

Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to

input “H” to ACK signal after D0, and to start SDA at SCL signal “H”.

・

Sequential read is ended by stop condition where “H” is input to ACK signal after arbitrary D0 and SDA is started at SCL

signal “H”.

It is necessary to input “H”

to the last ACK.

It is necessary to input “H”

to the last ACK.

W

R

I

T

E

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

WORD

ADDRESS(n)

SDA

LINE

A

C

K

A

C

K

DATA(n)

A

C

K

SLAVE

ADDRESS

10

0

1

PＳ

0

A2

WA

7

0

D0

SLAVE

ADDRESS

10

0

10

A2

S

T

A

R

T

D7

R

/

W

R

E

A

D

WA

0

0

A2

D7

1

1

0

0

R

E

A

D

S

T

A

R

T

R

/

W

S

T

O

P

DATA

SDA

LINE

SLA VE

ADDRES S

PS

D0

A

C

K

A

C

K

R

E

A

D

S

T

A

R

T

R

/

W

A

C

K

S

T

O

P

DATA(n)

SDA

LINE

A

C

K

A

C

K

DATA(n+x)

A

C

K

SLAVE

ADDRESS

10

0

1

PS

0

A2

D0

D7

D0

D7

Fig.39 Random Read cycle

Fig.40 Current read cycle

Fig.41 Sequential read cycle

1 0

0

1

PS

0

A2

Fig.42 Difference of slave address of each type

Note)