Technical Note

BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series

30/40

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2011.02 - Rev.F

© 2011 ROHM Co., Ltd. All rights reserved.

4) Write enable (WEN) / disable (WDS) cycle

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At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is

necessary to execute the write enable command. And, once this command is executed, it is valid unitl the write disable

command is executed or the power is turned off. However, the read command is valid irrespective of write enable /

disable command. Input to SK after 6 clocks of this command is available by either “H” or “L”, but be sure to input it.

○

When the write enable command is executed after power on, write enable status gets in. When the write disable

command is executed then, the IC gets in write disable status as same as at power on, and then the write command is

cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when

the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the

write disable command after completion of write.

●

Application

1) Method to cancel each command

○

READ

○

WRITE, WRAL

*1 Address is 8 bits in BR93H56/66-WC

Address is 10 bits in BR93H76/86-WC

*2 27 clocks in BR93H56/66-WC

29 clocks in BR93H76/86-WC

*3 28 clocks in BR93H56/66-WC

30 clocks in BR93H76/86-WC

Fig.34 READ cancel available timing

Fig.35 WRITE, WRAL cancel available timing

BR93H56/66-WC : n=11

BR93H76/86-WC : n=13

a：From start bit to 27 clock rise

Cancel by CS=“L”

b：27 clock rise and after *

2

Cancellation is not available by any means. If Vcc is made OFF in this area,

designated address data is not guaranteed, therefore write once again.

c：28 clock rise and after *

3

Cancel by CS=“L”

However, when write is started in b area (CS is ended), cancellation is not

available by any means.

And when SK clock is input continuously, cancellation is not available.

Start bit

Ope code

Address

Data

1bit

2bit

8bit

16bit

Cancel is available in all areas in read mode.

●

Method to cancel：cancel by CS=“L”

*1

*1 Address is 8 bits in BR93H56-WC, and BR93H66-WC.

Address is 10 bits in BR93H76-WC, and BR93H86-WC.

Start bit

Ope code

Address

Data

tE/W

a

*1

1bit

2bit

8bit

16bit

C

SK

・

D1

Enlarged figure

D0

DI

26

27

b

28

29

a

b

c

Note 1) If Vcc is made OFF in this area,

designated address data is not guaranteed,

therefore write once again.

Note 2) If CS is started at the same timing as that of

the SK rise, write execution/cancel becomes

unstable, therefore, it is recommended to fail in

SK=”L” area. As for SK rise, recommend timing of

tCSS/tCSH or higher.

CS

1

2

1

5

High-Z

0

0

SK

DI

DO

n

3

4

6

7

8

ENABLE=1 1

DISABLE=0 0

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Fig. 33 Write enable (WEN) / disable (WDS) cycle